Taiwan Semiconductor Manufacturing Comp. Ltd.

TSMC China Company Limited

Ming-Fang Lai

Hang Fan

Yi-Hsun Wu

Liang-Yu Su

Ching-Yun Chang

Yi-Feng Chang

Guan-Yu Chen

Shui-Ming Cheng

Jam-Wem Lee

Wun-Jie Lin

Li-Wei Chu

Ming-Cheng Lin

Tao Yi Hung

A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.

Electrostatic discharge (ESD) protection circuit and method of operating the same

The present disclosure provides an electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit, a second trigger circuit, a first discharge component and a second discharge component. The first trigger circuit includes a first GaN based transistor, including a first source/drain and a second source/drain coupled to the first reference terminal and a gate coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a terminal coupled to the first reference terminal via the second voltage divider. The first discharge component includes a gate coupled between the first trigger circuit and the first voltage divider. The second discharge component includes a gate coupled between the second trigger circuit and the second voltage divider.

Electrostatic discharge protection circuit and semiconductor circuit

An electrostatic discharge protection circuit includes an electrostatic discharge clamp between a first rail and a second rail, a trigger device configured to activate the electrostatic discharge clamp in response to an electrostatic discharge event, and a charge dissipation element between the first rail and the second rail to dissipate a residual charge at an input of the trigger device.

Charge dissipation element for ESD protection

The present disclosure provides a electrostatic discharge (ESD) protection circuit, coupled between a first reference terminal and a second reference terminal; the ESD protection circuit includes a first voltage divider, a second voltage divider, a first trigger circuit and a second trigger circuit. The first trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the first reference terminal, and the second terminal is coupled to the second reference terminal via the first voltage divider. The second trigger circuit includes a first terminal and a second terminal, wherein the first terminal is coupled to the second reference terminal, the second terminal is coupled to the first reference terminal via the second voltage divider, and the second trigger circuit and the first trigger circuit are in parallel connection.

An integrated circuit includes a semiconductor substrate, devices, first tap regions, and second tap regions. The devices are over the semiconductor substrate. The first tap regions are over the semiconductor substrate along a first direction. The second tap regions are over the semiconductor substrate along the first direction. A first pitch between adjacent two of the first tap regions in the first direction is greater than a second pitch between adjacent two of the second tap regions in the first direction.

Integrated circuit having latch-up immunity

A device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage at a first terminal and receive a second voltage at a second terminal and includes a first trigger circuit and a first resistor. The first trigger circuit includes a first input terminal and a first output terminal. The first input terminal is configured to receive the first voltage. The first resistor is coupled between the first output terminal and the second terminal. When the first voltage received at the first terminal is a first overvoltage and a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch.

Device and method for electrostatic discharge protection

A device is disclosed herein. The device includes an electrostatic discharge (ESD) protection switch and an ESD driver. The ESD driver is configured to receive a first voltage and a second voltage. When a voltage difference between the first voltage and the second voltage is higher than a first voltage threshold, the ESD driver outputs a first trigger signal to turn on the ESD protection switch. When the voltage difference between the first voltage and the second voltage is lower than a second voltage threshold, the ESD driver outputs a second trigger signal to turn on the ESD protection switch.

A method for forming an integrated circuit (IC) is provided. The method includes obtaining an IC design; generating a layout according to the IC design; calculating a score of a region in the layout based on voltage levels in the region; and fabricating a semiconductor device according to the layout when the score of the region in the layout is equal to or less than a threshold value.

Integrated circuit and method for forming the same

Electrostatic discharge protection circuit

A circuit including a discharging device, a resistive element and a bypass device is disclosed. The discharging device is disposed between a first voltage bus and a second voltage bus. The resistive element is configured to activate the discharging device in response to a high-to-low electrostatic discharge (ESD) event during which the first voltage bus is high in potential relative to the second voltage bus. The bypass device is configured to bypass the resistive element and activate the discharging device in response to a low-to-high ESD event during which the second voltage bus is high in potential relative to the first voltage bus.

Circuit, system and method for electrostatic discharge (ESD) protection

The present disclosure relates to an electrostatic discharge (ESD) protection circuit including a dynamic field plate bias circuit, and associated methods. In some embodiments, the ESD protection circuit includes a bipolar junction transistor (BJT) based ESD protection circuit including a field plate configured to increase a breakdown voltage of the BJT based ESD protection circuit. The ESD protection circuit also includes a dynamic field plate bias circuit coupled to the field plate of the BJT based ESD protection circuit. The dynamic field plate bias circuit is configured to provide the field plate a field plate bias at transient opposite to a field plate bias at a normal operation. The transient bias reduces a trigger voltage of the BJT based ESD protection circuit and increases a shunt current of the BJT based ESD protection circuit during the ESD event. Thereby, ESD protection reliability is improved.

Dynamic ESD protection scheme

The present disclosure relates to a semiconductor device. The semiconductor device includes a substrate, a first doping region, a second doping region, a third doping region, a first transient block unit and a second transient block unit. The first doping region is in the substrate. The second doping region is in the first doping region. The third doping region is in the first doping region. The first transient block unit is electrically connected to the second doping region. The second transient block unit is electrically connected between the third doping region and the first transient block unit.

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Hsinchu, Taiwan

Ming-Fang Lai