Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Fa Chen

Hsien-Wei Chen

Sung-Feng Yeh

Chen-Hua Douglas Yu

Jie Chen

Tzuan-Horng Liu

Chao-Wen Shih

Sen-Bor Jan

Chih-Chia Hu

Ying-Ju Chen

Wen-Chih Chiou

Ching-Jung Yang

Chen-Shien Chen

Nien-Fang Wu

Wen-Ching Tsai

Ching-Pin Yuan

Hsien-Pin Hu

Yi-Hsiu Chen

Wen-Wei Shen

Jao Sheng Huang

Yu-Young Wang

Chao-Hsiang Yang

Min-Chien Hsiao

Jian-Wei Hong

Chun-Chiang Kuo

Jing-Cheng Lin

Shau-Lin Shue

Hsiao-Tsung Yen

Chen-Cheng Kuo

Yung-Chi Lin

Chin-Wei Kuo

Sally Liu

Jhe-Ching Lu

I-Ching Lin

Jiun Ren Lai

Jiun-Heng Wang

Hui-Wen Liu

Wensen Hung

Tsung-Yu Chen

Rung-De Wang

Yung-Jean Lu

Chang-Ching Yu

Wen-Sen Lu

Chi-Hwang Tai

Sheng-An Kuo

Meng-Wei Chiang

Chuan-An Cheng

Ying-Ching Shih

Po-Hsiang Huang

Yi-Kan Cheng

Fong-yuan Chang

Chin-Chou Liu

Shih-Shiung Chen

Ying-Chen Chao

Jen-Li Hu

Noor Mohamed Ettuveettil

Chung-Shi Liu

Shin-Puu Jeng

Ming-Da Cheng

Hsiu-Jen Lin

Chih-Hua Chen

Meng-Tse Chen

Sung-Hui Huang

Yao-Chun Chuang

Hui-Min Huang

Ming-Yen Chiu

Yuan-Hung Liu

Chia-Hsiang Chen

Sheng-Yuan Lin

Yao-Hwan Kao

De-Yuan Lu

Chih-Chien Hung

Fu-Tien Wong

Ho-Ku Lan

Ta-Hao Sung

Chin-Shyh Wang

Cheng-Feng Chen

Jia-Sheng Lee

Ming-Chang Huang

Wen-Chih Chiu

Chia-Yen Lee

A semiconductor device and method of manufacture are provided wherein the semiconductor device includes a first system on chip device bonded to a first memory device, a second system on chip device bonded to the first memory device, a first encapsulant surrounding the first system on chip device and the second system on chip device, a second encapsulant surrounding the first system on chip device, the second system on chip device, and the first memory device, and a through via extending from a first side of the second encapsulant to a second side of the first encapsulant, the through via being located outside of the first encapsulant.

Method of manufacturing semiconductor devices with system on chip devices

A structure includes a first die and a second die. The first die includes a first bonding layer having a first plurality of bond pads disposed therein and a first seal ring disposed in the first bonding layer. The first bonding layer extends over the first seal ring. The second die includes a second bonding layer having a second plurality of bond pads disposed therein. The first plurality of bond pads is bonded to the second plurality of bond pads. The first bonding layer is bonded to the second bonding layer. An area interposed between the first seal ring and the second bonding layer is free of bond pads.

Seal ring for hybrid-bond

A semiconductor structure including a first semiconductor die and a second semiconductor die is provided. The first semiconductor die includes a first bonding structure. The second semiconductor die is bonded to the first bonding structure of the first semiconductor die. The first bonding structure includes a first dielectric layer, a second dielectric layer covering the first dielectric layer, and first conductors embedded in the first dielectric layer and the second dielectric layer, wherein each of the first conductors includes a first conductive barrier layer covering the first dielectric layer and a first conductive pillar disposed on the first conductive barrier layer, and the first conductive pillars are in contact with the second dielectric layer.

Semiconductor structure

An integrated circuit component includes a semiconductor substrate, conductive pads, a passivation layer and conductive vias. The semiconductor substrate has an active surface. The conductive pads are located on the active surface of the semiconductor substrate and electrically connected to the semiconductor substrate, and the conductive pads each have a contact region and a testing region, where in each of the conductive pads, an edge of the contact region is in contact with an edge of the testing region. The passivation layer is located on the semiconductor substrate, where the conductive pads are located between the semiconductor substrate and the passivation layer, and the testing regions and the contact regions of the conductive pads are exposed by the passivation layer. The conductive vias are respectively located on the contact regions of the conductive pads.

Integrated circuit component and package structure having the same

A semiconductor device includes a first functional block and a second functional block. The first functional block includes a first substrate, a first device layer, a first interconnect structure and a plurality of first bonding patterns, and the first interconnect structure includes a plurality of first conductive patterns. The first bonding patterns are irregularly arranged. The second functional block is bonded to the first functional block. The second functional block includes a second substrate, a second device layer, a second interconnect structure and a plurality of second bonding patterns, and the second bonding patterns are in direct contact with the first bonding patterns.

Semiconductor device and method of forming the same

A semiconductor structure includes a first semiconductor substrate, a first interconnect structure disposed below the first semiconductor substrate, a through substrate via (TSV) penetrating through the first semiconductor substrate and extending into the first interconnect structure, and a first bonding conductor disposed below the first interconnect structure and electrically coupled to the TSV through the first interconnect structure. The TSV includes a first surface in the first interconnect structure and a second surface opposite to the first surface, and the first bonding conductor includes a first bonding surface facing away the first interconnect structure. In a view, a boundary of the first bonding surface of the first bonding conductor overlaps a boundary of the first surface of the TSV.

Semiconductor structure and manufacturing method thereof

A semiconductor structure includes a first die and a plurality of first dummy pads. The first die includes a first interconnect structure and a first active pad electrically connected to the first interconnect structure. The first dummy pads laterally surround the first active pad and are electrically floating.

A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.

Buffer design for package integration

A package structure including a device die structure, an insulating encapsulant, and a first redistribution circuit is provided. The device die structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die is stacked over and electrically connected to the second semiconductor die. The insulating encapsulant laterally encapsulates the device die structure. The insulating encapsulant includes a first encapsulation portion and a second encapsulation portion connected to the first encapsulation portion. The first encapsulation portion is disposed on the second semiconductor die and laterally encapsulates the first semiconductor die. The second encapsulation portion laterally encapsulates the first insulating encapsulation and the second semiconductor die. The first redistribution circuit structure is disposed on the device die and a first surface of the insulating encapsulant, and the first redistribution circuit structure is electrically connected to the device die.

Package structure

A package includes a carrier substrate, a first die, and a second die. The first die and the second die are stacked on the carrier substrate in sequential order. The first die includes a first bonding layer, a second bonding layer, and an alignment mark embedded in the first bonding layer. The second die includes a third bonding layer. A surface of the first bonding layer form a rear surface of the first die and a surface of the second bonding layer form an active surface of the first die. The rear surface of the first die is in physical contact with the carrier substrate. The active surface of the first die is in physical contact with the third bonding layer of the second die.

Package

A package includes an interposer having a first redistribution structure; a first die directly bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die directly bonded to the first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.

Molded dies in semiconductor packages and methods of forming same

A semiconductor package including hybrid bonding and solder bonding along a first interface and methods of forming the same are disclosed. In an embodiment, a package includes a first interposer, the first interposer including a first redistribution structure; a first die bonded to a first surface of the first redistribution structure with a dielectric-to-dielectric bond and a metal-to-metal bond; a second die bonded to the first surface of the first redistribution structure with a first solder bond; an encapsulant around the first die and the second die; and a plurality of conductive connectors on a second side of the first redistribution structure opposite to the first die and the second die.

Semiconductor packages including mixed bond types and methods of forming same

A semiconductor structure includes an encapsulated die including an electronic die and an insulating layer laterally covering the electronic die, and a photonic die coupled to the encapsulated die. The photonic die includes an optical device in proximity to an edge coupling facet of the photonic die. In a top-down view, a boundary of the electronic die is within a boundary of the insulating layer, and the boundary of the insulating layer is within a boundary of the photonic die.

Semiconductor structure having photonic die and electronic die

A semiconductor device including a test pad contact and a method of manufacturing the semiconductor device are disclosed. In an embodiment, a semiconductor device may include a first metal feature and a second metal feature disposed in a single top metal layer over a substrate. A test pad may be formed over and electrically connected to the first metal feature. A first passivation layer may be formed over the second metal feature and the test pad and may cover top and side surfaces of the test pad. A first via may be formed penetrating the first passivation layer and contacting the test pad and a second via may be formed penetrating the first passivation layer and contacting the second metal feature.

Semiconductor device and method of manufacture

A semiconductor package includes a first die including an optical coupler, a second die disposed on the first die, and a transparent encapsulation material disposed on the first die. The second die includes a substrate and a transparent portion disposed within the substrate and optically coupled to the optical coupler. The transparent encapsulation material extends along sidewalls of the substrate of the second die.

Semiconductor package

Growing community of inventors

Taichung, Taiwan

Ming-Fa Chen