National Yang Ming Chiao Tung University

Amazing Microelectronic Corporation

United Microelectronics Corp.

Faraday Technology Corporation

Taiwan Semiconductor Manufacturing Comp. Ltd.

Novatek Microelectronics Corp.

Global Unichip Corporation

Industrial Technology Research Institute

Chunghwa Picture Tubes, Ltd.

Winbond Electronics Corporation

Vanguard International Semiconductor Corporation

Elan Microelectronics Corporation

Ming-Dou Ker

Chun-Yu Lin

Chang-Tzu Wang

Ryan Hsin-Chin Jiang

Fu-Yi Tsai

Che-Hao Chuang

Wen-Tai Wang

Tzu-Chien Tzeng

James Jeng-Jie Peng

Woei-Lin Wu

Ju-Lin Huang

Yuan-Wen Hsiao

Wen-Yi Chen

Federico Agustin Altolaguirre

Jie-Ting Chen

Kun-Hsien Lin

Keko-Chun Liang

Yeh-Ning Jou

Tung-Yang Chen

Hsin-Chin Jiang

Hwa-Chyi Chiou

Jung-Sheng Chen

Yeh-Jen Huang

Ming-Ying Kuo

Shih-Hung Chen

Yan-Hua Peng

Chun-Yuan Hsu

Chia-Ku Tsai

Chih-Kang Deng

Ming-Chun Chou

Wei-Ling Chen

Chia-Wei Hung

Wu-Tsung Hsihe

Hui-Wen Tsai

Yi-Ju Li

Li-Chin Yu

An electrostatic discharge (ESD) protection device and an operation method of the ESD protection device are provided. The ESD protection device includes an ESD current rail, an ESD protection element string, and a bias circuit. A first end and a second end of the ESD protection element string are electrically connected to the ESD current rail and a signal pad, respectively. The ESD protection element string includes a first ESD protection element and a second ESD protection element that are serially connected. The bias circuit is electrically connected to the ESD protection element string to provide a bias voltage to a common connection node between the first ESD protection element and the second ESD protection element.

Device and operation method for electrostatic discharge protection

The present disclosure relates to a high-voltage generator with multi-stage selection in low-voltage transistor process which include a boosted circuit, a plurality of switch and a feedback circuit. The boosted circuit includes multiple charge pump, so that can generate a DC output voltage higher or lower than the input signal. Turning on or turning off each switch controlled by a control signal respectively. Both ends of the circuit is connected to the output end of the high-voltage generator and charge pumps. By controlling the turning on or turning off each switch, it determines the magnitude of the boost and it also can ensure that switches will not be damaged due to excessive voltage difference.

High-voltage generator with multi-stage selection in low-voltage transistor process

In the disclosure, an electrostatic discharge (ESD) protection circuit is coupled between a first power rail and a second power rail to discharge any ESD stress. The ESD protection circuit includes a detection circuit, a triggering circuit, and a dual silicon controlled rectifier (DSCR) device. When an ESD stresses is being applied to the first or second power rail, the detection circuit may first detect the ESD stresses and output a detection signal to the triggering circuit. The triggering circuit generates a triggering signal based on the detection signal and the polarity of the ESD stress. Then, the DSCR device is symmetrically triggered based on the triggering signal received at a common node between at least two transistors of the same type. The exemplary ESD protection circuit may be implemented in nanoscale manufactured integrated circuit and achieve good ESD robustness while maintaining low standby leakage current and relatively small silicon footprint.

Electrostatic discharge protection circuit

A silicon controlled rectifier including a semiconductor substrate, first and second semiconductor wells, first and second semiconductor regions, third and fourth semiconductor regions and a silicide layer is provided. The first and the second semiconductor wells are formed in the semiconductor substrate. The first and the second semiconductor regions are respectively formed in the first and the second semiconductor wells in spaced apart relation. The third and the fourth semiconductor regions are respectively formed in the first and the second semiconductor wells. The silicide layer is formed on the third and the fourth semiconductor regions. The silicon controlled rectifier is at least suitable for high frequency circuit application. The silicon controlled rectifier has a relatively low trigger voltage, a relatively high electrostatic discharge level, and a relatively low capacitance.

Silicon controlled rectifier

In a test method for eliminating electrostatic charges, at least one test process is firstly performed by a test equipment comprising a tester and a platform, and electrostatic charges are generated on the test equipment in the test process. In the test process, the tester contacts and tests at least one tested integrated circuit (IC) on a test area of the platform, and then the tested IC is removed from the tester and the test area. Next, a conduction device which is grounded is moved to the test area, so that the tester contacts the conduction device to discharge the electrostatic charges to ground. Next, the conduction device is removed from the tester and the test area. Finally, the method returns to the test process to test the next tested IC.

Test method for eliminating electrostatic charges

A diode includes a substrate, a first insulating layer, a second insulating layer, a well, a deep doped region, a first doped region, and a second doped region. The first insulating layer is disposed on the substrate. The second insulating layer is disposed on the substrate, and defines a cell region with the first insulating layer. The well is disposed on the substrate and beneath the cell region. The deep doped region is disposed in the well and beneath the cell region. The first doped region is disposed in the cell region and on the deep doped region. The second doped region is disposed adjacent to the first doped region. The second doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region and the first doped region.

Diode, diode string circuit, and electrostatic discharge protection device having doped region and well isolated from each other

A self-balanced diode device includes a substrate, a doped well, at least one first conductivity type heavily doped fin and at least two second conductivity type heavily doped fins. The doped well is arranged in the substrate. The first conductivity type heavily doped fin is arranged in the doped well, arranged in a line along a first direction, and protruded up from a surface of the substrate. The second conductivity type heavily doped fins is arranged in the doped well, arranged in a line along a second direction intersecting the first direction, respectively arranged at two opposite sides of the first conductivity type heavily doped fin, and protruded up from the surface of the substrate. Each second conductivity type heavily doped fin and the first conductivity type heavily doped fin are spaced at a fixed interval.

Self-balanced diode device

A gate-bounded silicon controlled rectifier includes a substrate, an N-type well region, a P-type well region, a first N-type semiconductor region, a first P-type semiconductor region, a second N-type semiconductor region, a second P-type semiconductor region and a third semiconductor region. The N-type well region and the P-type well region are disposed in the substrate. The first N-type semiconductor region is disposed in the N-type well region. The first P-type semiconductor region is disposed in the P-type well region. The second N-type semiconductor region is disposed in the P-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The second P-type semiconductor region is disposed in the N-type well region and located between the first N-type semiconductor region and the first P-type semiconductor region. The third semiconductor region is located between the second N-type semiconductor region and the second P-type semiconductor region.

Gate-bounded silicon controlled rectifier

A self-balanced silicon-controlled rectification device includes a substrate, an N-type doped well, a P-type doped well, at least one heavily doped clamping fin, at least one first P-type heavily doped fin, and at least one first N-type heavily doped fin. The N-type doped well and the P-type doped well are arranged in the substrate. The heavily doped clamping fin is arranged in the N-type doped well and the P-type well and protruded up from a surface of the substrate. The first P-type heavily doped fin and the first N-type heavily doped fin are respectively arranged in the N-type doped well and the P-type doped well, and protruded up from the surface of the substrate. The abovementioned elements forms silicon-controlled rectifiers (SCRs) are forward biased to generate uniform electrostatic discharge (ESD) currents through the SCRs.

Self-balanced silicon-controlled rectification device

A bipolar transistor device includes a substrate and at least one first transistor unit. The first transistor unit includes a first doped well of first conductivity type, at least one first fin-based structure and at least one second fin-based structure. The first fin-based structure includes a first gate strip and first doped fins arranged in the first doped well, and the first gate strip is floating. The second fin-based structure includes a second gate strip and second doped fins arranged in the first doped well, and the second gate strip is floating. The first doped fins, the second doped fins and the first doped well form first BJTs, and the first doped fins and the second doped fins are respectively coupled to high and low voltage terminals.

Bipolar transistor device

A defibrillator device is provided. The defibrillator device includes a first electrode, a second electrode, a readout module, a USB interface, a voltage converter and a stimulation module. When the first and second electrodes contact the chest of a patient, the readout module obtains a physiologic rhythm signal of the patient and provides a heart rhythm signal according to the first physiologic rhythm signal. According to a first voltage from a portable electronic device, the voltage converter generates a second voltage when the first USB interface is coupled to the portable electronic device, wherein the second voltage is larger than the first voltage. When the physiologic rhythm signal indicates that cardiac arrhythmia is present in the patient, the stimulation module provides an electric shock energy to the chest of the patient via the first and second electrodes according to the second voltage.

Defibrillator device

An active guard ring structure is provided, which is applicable to improving latch-up immunity during the latch-up current test (I-test). The proposed active guard ring structure comprises an I/O circuit and an active protection circuit, wherein the I/O circuit receives a trigger current via an input pad and generates a corresponding bulk current since being triggered. The active protection circuit, connected between the I/O circuit and a core circuit, detects whether the trigger current is a positive or negative current pulse. When an intensity of the trigger current is larger than a threshold value, the active protection circuit controls the I/O circuit to provide a sink or compensation current so as to neutralize the bulk current and to reduce the net current flowing into or sourced from the core circuit, thereby increasing the latch-up resistance and immunity of the core circuit.

Active guard ring structure to improve latch-up immunity

A silicon controlled rectifier includes a substrate, a well, a deep doped region, a first doped region, a second doped region, a third doped region, and a fourth doped region. The well is disposed on the substrate and underneath a cell region. The deep doped region is disposed in the well. The first doped region has a first conductivity type, and is disposed in the well. The second doped region and third doped region have the first conductivity type and are disposed on the deep doped region. The fourth doped region has a second conductivity type, and is disposed between the second doped region and the third doped region. The fourth doped region is disposed on the deep doped region, and is electrically isolated from the well through the deep doped region, the second doped region, and the third doped region.

A three-dimension (3D) integrated circuit (IC) package is disclosed. The 3D IC package has a package substrate having a surface. At least one integrated circuit (IC) chip with or without suppressing a transient voltage and at least one transient voltage suppressor (TVS) chip are arranged on the surface of the substrate and electrically connected with each other. The IC chip is independent from the TVS chip. The IC chip and the TVS chip stacked on each other are arranged on the package substrate. Alternatively, the IC chip and the TVS chip are together arranged on an interposer formed on the package substrate.

Three-dimension (3D) integrated circuit (IC) package

An electrostatic discharge (ESD) protection circuit, suitable for an input stage circuit including a first N channel metal oxide semiconductor (NMOS) transistor, is provided. The ESD protection circuit includes an P channel metal oxide semiconductor (PMOS) transistor and an impedance device, in which the PMOS transistor has a source coupled to a gate of the first NMOS transistor, and a drain coupled to a source of the first NMOS transistor, and the impedance device is coupled between a gate of the PMOS transistor and a first power rail to perform a initial-on ESD protection circuit. The ESD protection circuit formed by the PMOS transistor and the resistor is capable of increasing the turn-on speed of the ESD protection circuit and preventing the input stage circuit from a CDM ESD event.

Growing community of inventors

Hsinchu County, Taiwan

Ming-Dou Ker