Mediatek Corporation

International Business Machines Corporation

Mediatek Singapore Pte. Ltd.

Ming-Da Tsai

Chien-Wei Tseng

Chien-Cheng Lin

Arun Sridhar Natarajan

Bernard Mark Tenbroek

Po-Sen Tseng

Yangjian Chen

Jui-Chih Kao

Ian Tseng

Jing-Hong Conan Zhan

Cheng-Chou Hung

Yen-Horng Chen

Chih-Fan Liao

Tao-Yi Lee

Scott Kevin Reynolds

Yu-Hsin Lin

Brian Allan Floyd

Tung-Hsing Lee

Alberto Valdes-Garcia

Siu-Chuang Ivan Lu

Chih-Hung Lee

Jie-Wei Lai

Jui-Lin Hsu

George Chien

Sean Timothy Nicolson

Chih-Chun Hsu

Yuan-Yu Fu

Li-Shin Lai

Lai-Ching Lin

Ping-Yu Chen

Tzu-Yu Yeh

Mohammed Fathey Abdelfattah Hassan

Aspects of the disclosure provide methods and apparatuses for generating an internal reset signal that is synchronous to a clock signal. In some embodiments, an apparatus includes a clock switch circuit and a plurality of serially coupled D flip-flops (DFFs). The clock switch circuit receiving the clock signal can output the clock signal in an on state and block the clock signal in an off state. The plurality of serially coupled DFFs are coupled to the clock switch circuit and driven by the clock signal. If an external reset signal is enabled, the plurality of serially coupled DFFs can enable the internal reset signal. If the external reset signal is disabled, after a predefined number of clock signal cycles, the plurality of serially coupled DFFs can disable the internal reset signal.

Phase synchronized LO generation

A quadrature transmitter includes a first and second matched transmitter path. Each transmitter path receives respective sets of quadrature baseband signals. At least one local oscillator port receives respective sets of quadrature LO signals. Mixer stage(s) respectively multiply the sets of quadrature baseband signals with the respective sets of quadrature LO signals to produce a respective output radio frequency signal. A combiner combines the output RF signals. The first set of quadrature signals is a substantially 45&#xb0; phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45&#xb0; phase shifted version of the second set of quadrature LO signals. A baseband error correction circuit corrects a phase error between the quadrature baseband signals at baseband and a LO error correction circuit corrects a phase error between the quadrature baseband signals at a LO frequency.

Quadrature transmitter, wireless communication unit, and method for spur suppression

A radio-frequency (RF) power amplifier includes a matching network comprising at least one matching network circuit corresponding to at least one symmetry node, at least one detector for detecting power of a detected signal at the symmetry node of the matching network, and generating at least one control signal according to the power of the detected signal, wherein the detected signal is an odd harmonic of an RF signal when the RF power amplifier operates in a differential mode or an even harmonic of the RF signal when the RF power amplifier operates in a common mode, and at least one adjusting circuit for adjusting the RF signal according to the at least one control signal.

Matching network circuit and radio-frequency power amplifier with odd harmonic rejection and even harmonic rejection and method of adjusting symmetry of differential signals

A harmonic-rejection mixer apparatus includes a mixing circuit and a combining circuit. The mixing circuit receives mixes an input signal and a first local oscillator (LO) signal to generate a first output signal, and mixes the same input signal and a second LO signal to generate a second output signal, wherein the first LO signal and the second LO signal have a same frequency but different phases. The combining circuit combines the first output signal and the second output signal, wherein harmonic rejection is at least achieved by combination of the first output signal and the second output signal.

Phase-rotated harmonic-rejection mixer apparatus

A power amplifier system includes a differential power amplifier and a bias circuit. The differential power amplifier is arranged for receiving a differential input pair to generate an output signal. The bias circuit is arranged for generating a bias voltage to bias the differential power amplifier, and the bias circuit comprises a source follower for receiving a reference voltage to generate the bias voltage.

Power amplifier system and associated bias circuit

An integrated circuit apparatus includes a substrate, an IC chip disposed above the substrate, and an electromagnetic shielding layer disposed on a surface of the substrate. The IC chip includes an electromagnetic coupling device. The electromagnetic shielding layer and the electromagnetic coupling device partially overlap in a vertical projection direction of the surface of the substrate.

Integrated circuit apparatus

A control circuit of a power amplifier includes a peak detector, a first comparator, a first current source, a second comparator, a second current source and a bias circuit. The peak detector is arranged for detecting an amplitude of an input signal. The first comparator is arranged for comparing the amplitude of the input signal with a first threshold to generate a first comparing result. The first current source is arranged for generating a first current according to the first comparing result The second comparator is arranged for comparing the amplitude of the input signal with a second threshold to generate a second comparing result. The second current source is arranged for generating a second current according to the second comparing result. The bias circuit is arranged for generating a bias voltage according to the first current and the second current to the power amplifier.

Power amplifier system and associated control circuit and control method

The present invention provides a control circuit to stabilize an output power of a power amplifier. The control circuit comprises a voltage clamping loop, a current clamping loop and a loop for reducing power variation under VSWR, where the voltage clamping loop is used to clamp an output voltage of the power amplifier within a defined voltage range, the current clamping loop is used to clamp a current of the power amplifier within a defined current range, and the loop for reducing power variation under VSWR is implemented by an impedance detector to compensate the output power under VSWR variation.

Amplifier system, controller of main amplifier and associated control method

A quadrature transmitter is described that comprises: a first transmitter path and a second transmitter path that are matched. Each transmitter path comprises: at least one input arranged to receive respective first or second sets of quadrature baseband signals; at least one local oscillator, LO, port configured to receive respective first and second sets of quadrature LO signals; at least one mixer stage coupled to the at least one input and configured to respectively multiply the sets of quadrature baseband signals with the respective first or second sets of quadrature LO signals to produce a respective output radio frequency, RF, signal; and a combiner configured to combine the output radio frequency signals of the first transmitter path and the second transmitter path. The first set of quadrature signals is a substantially 45&#xb0; phase shifted version of the second set of quadrature signals; and the first set of quadrature LO signals is a reverse substantially 45&#xb0; phase shifted version of the second set of quadrature LO signals.

A compensation circuit of a power amplifier includes a varactor, a voltage sensor and a control circuit. The varactor is coupled to an input terminal of the power amplifier. The voltage sensor is arranged for detecting an amplitude of an input signal of the power amplifier to generate a detecting result. The control circuit is coupled to the varactor and the voltage sensor, and is arranged for controlling a bias voltage of the varactor to adjust a capacitance of the varactor according to the detecting result.

Compensation circuit of power amplifier and associated compensation method

A matching network circuit for RF power amplifier circuit capable of odd harmonic rejection and even harmonic rejection in the differential mode and the common mode, respectively. The matching network circuit includes a differential mode filter with a differential resonant frequency and a passive component coupled to a virtual short circuit node at the differential mode filter, wherein a common mode filter with a common resonant frequency includes the differential mode filter and the passive component. As a result, two notch filters with different resonant frequencies are utilized for the common mode and the differential mode, respectively.

A semiconductor integrated circuit includes an inductor and a plurality of high permeability patterns. The inductor includes one conductive loop. The high permeability patterns are disposed adjacent to the conductive loop.

Semiconductor integrated circuit

A power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding; wherein, the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding. In addition, there is provided a radio frequency (RF) transmitter having a power combiner, where the power combiner includes a planar figure-8 shaped primary winding and a planar figure-8 shaped secondary winding, wherein the planar figure-8 shaped primary winding is substantially overlaid with the planar figure-8 shaped secondary winding.

Radio frequency transmitter, power combiners and terminations therefor

A hybrid passive device for synergizing at least one passive component which resides in at least one technology is provided. The hybrid passive device includes a first passive component and a second passive component. The first passive component resides in a first technology of the at least one technology and/or a second technology of the at least one technology, the second technology is different from the first technology, and a technology boundary is arranged between the second technology and the first technology. The second passive component of the at least one passive component is different from the first passive component. The second passive component resides in the first technology and/or the second technology, and the first passive component and the second passive component are electromagnetically coupled to each other through the technology boundary.

Hybrid passive device and hybrid manufacturing method

A diplexer, for coupling a first radio frequency (RF) signal corresponding to a first carrier frequency and a second RF signal corresponding to a second carrier frequency is disclosed. The diplexer includes a first port arranged to couple the first RF signal; a second port arranged to couple the second RF signal; a third port capable of connecting an antenna; a first impedance unit coupled to the first port and the third port; and a second impedance unit coupled to the second port and the third port; wherein the first port, the second port and the third port are coupled to a direct current (DC) ground; wherein the first impedance unit is arranged to provide an first open-circuit impedance against the second RF signal, and the second impedance unit is arranged to provide a second open-circuit impedance against the first RF signal.

Growing community of inventors

Miaoli County, Taiwan

Ming-Da Tsai