Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Da Cheng

Chung-Shi Liu

Wei-Hung Lin

Chih-Wei Lin

Wen-Hsiung Lu

Chen-Hua Douglas Yu

Meng-Tse Chen

Hsiu-Jen Lin

Hui-Min Huang

Kuei-Wei Huang

Mirng-Ji Lii

Wei-Yu Chen

Chun-Cheng Lin

Ching-Hua Hsieh

Chen-Shien Chen

Chih-Fan Huang

Yu-Peng Tsai

Hsien-Wei Chen

Cheng-Ting Chen

Hsuan-Ting Kuo

Ai-Tee Ang

Chang-Jung Hsueh

Po-Hao Tsai

Yu-Hsiang Hu

Ching-Wen Hsiao

Tsung-Yuan Yu

Shing-Chao Chen

Hung-Jui Kuo

Bor-Ping Jang

Chih-Hua Chen

Hao-Yi Tsai

Tin-Hao Kuo

Chien Ling Hwang

Chun-Hung Lin

Yu-Feng Chen

Yi-Wen Wu

Chih-Chiang Tsao

Tsung-Ding Wang

Ming-Che Ho

Hao-Jan Pei

Hong-Seng Shue

Han-Ping Pu

Ming-Chih Yew

Yu-Chih Huang

Yeong-Jyh Lin

Tsung-Hsien Chiang

Chia-Lun Chang

Chang-Chia Huang

Sheng-Hsiang Chiu

Kai-Chiang Wu

Chien-Hsun Lee

Chen-Cheng Kuo

Tsung-Shu Lin

Sheng-Yu Wu

Chih-Hsuan Tai

Chien-Hsiun Lee

Cheng-Chung Lin

Yu-Chih Liu

Chien-Wei Lee

Chia-Wei Tu

Hung-Jen Lin

Ting-Ting Kuo

Ching-Yu Chang

An-Jhih Su

Kuo-Chung Yee

Chih-Hang Tung

Chun-Hung Chen

Chin-Yu Ku

Kuo-Ching Hsu

Sey-Ping Sun

Yu-min Liang

Chun-Hui Yu

Yi-Jen Lai

Ming-Hui Weng

Wei Sen Chang

Yang-Che Chen

Jiun Yi Wu

Chin-Fu Kao

Yi-Li Hsiao

Jung Wei Cheng

Yu-Min Liang

Kuo-Lung Pan

Chia-Shen Cheng

Song-Bor Lee

Kuang-Chun Lee

Ming-Fa Chen

Der-Chyang Yeh

Sung-Feng Yeh

Jui-Pin Hung

Chao-Wen Shih

Cheng-Lin Huang

Hui-Jung Tsai

Yao-Chun Chuang

Tzu-Yang Lin

Chita Chuang

Chen-Yu Liu

Chih-Hsien Lin

Wei-Li Huang

Meng-Wei Chou

A method includes forming a first package component, which formation process includes forming a first plurality of openings in a first dielectric layer, depositing a first metallic material into the first plurality of openings, performing a planarization process on the first metallic material and the first dielectric layer to form a plurality of metal pads in the first dielectric layer, and selectively depositing a second metallic material on the plurality of metal pads to form a plurality of bond pads. The first plurality of bond pads comprise the plurality of metal pads and corresponding parts of the second metallic material. The first package component is bonded to a second package component.

Heterogeneous bonding structure and method forming same

A method of manufacturing a bump structure includes forming a passivation layer over a substrate. A metal pad structure is formed over the substrate, wherein the passivation layer surrounds the metal pad structure. A polyimide layer including a polyimide is formed over the passivation layer and the metal pad structure. A metal bump is formed over the metal pad structure and the polyimide layer. The polyimide is a reaction product of a dianhydride and a diamine, wherein at least one of the dianhydride and the diamine comprises one selected from the group consisting of a cycloalkane, a fused ring, a bicycloalkane, a tricycloalkane, a bicycloalkene, a tricycloalkene, a spiroalkane, and a heterocyclic ring.

Bump structure and method of manufacturing bump structure

In a method of forming a heat dissipating structure for a semiconductor chip, a soldering material is disposed on a top surface of the semiconductor chip. A first region of metal plating is formed on a surface of a lid. The first region has a first width and a first length. The first width is larger than a second width of the top surface of the semiconductor chip and the first length is larger than a second length of the top surface of the semiconductor chip. The lid is placed over the semiconductor chip so that the first region of metal plating of the lid is disposed over the soldering material to bond the lid to the semiconductor chip by a soldering material layer having an inverted trapezoidal shape between the lid and the top surface of the semiconductor chip.

Inverted trapezoidal heat dissipating solder structure and method of making the same

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over the insulating layer. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure and method for forming the same

A method includes forming a seed layer over a first conductive feature of a wafer, forming a patterned plating mask on the seed layer, and plating a second conductive feature in an opening in the patterned plating mask. The plating includes performing a plurality of plating cycles, with each of the plurality of plating cycles including a first plating process performed using a first plating current density, and a second plating process performed using a second plating current density lower than the first plating current density. The patterned plating mask is then removed, and the seed layer is etched.

Redistribution lines having nano columns and method forming same

A method includes attaching a die to a thermal compression bonding (TCB) head through vacuum suction, wherein the die comprises a plurality of conductive pillars, attaching a first substrate to a chuck through vacuum suction, wherein the first substrate comprises a plurality of solder bumps, contacting a first conductive pillar of the plurality of conductive pillars to a first solder bump of the plurality of solder bumps, wherein contacting the first conductive pillar to the first solder bump results in a first height between a topmost surface of the first conductive pillar and a bottommost surface of the first solder bump, and adhering the first solder bump to the first conductive pillar to form a first joint, wherein adhering the first solder bump to the first conductive pillar comprises heating the TCB head.

Package bonding structures and method of formation

A method includes forming a metal seed layer over a first conductive feature of a wafer, forming a patterned photo resist on the metal seed layer, forming a second conductive feature in an opening in the patterned photo resist, and heating the wafer to generate a gap between the second conductive feature and the patterned photo resist. A protection layer is plated on the second conductive feature. The method further includes removing the patterned photo resist, and etching the metal seed layer.

Redistribution lines with protection layers and method forming same

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Bump structure and method of making the same

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.

Semiconductor device with inductive component and method of forming

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure with conductive pillar and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The first conductive structure has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive structure. The semiconductor device structure also includes a second conductive structure over the semiconductor substrate. The second conductive structure is substantially as wide as the first conductive structure, and the second conductive structure has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive structure. The first conductive structure is closer to a center point of the semiconductor substrate than the second conductive structure. The second protruding portion is wider than the first protruding portion, and bottoms of the first protruding portion and the second protruding portion are substantially level with each other.

Semiconductor device structure with conductive bumps

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Semiconductor package system and method

A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Semiconductor die including stress-resistant bonding structures and methods of forming the same

A method for forming a semiconductor structure is provided. The method includes forming a patterned photoresist layer over a substrate and removing the patterned photoresist layer using a photoresist stripping composition that is free of dimethyl sulfoxide. The photoresist stripping composition includes an organic alkaline compound including at least one of a primary amine, secondary amine, a tertiary amine or a quaternary ammonium hydroxide or a salt thereof, an organic solvent selected from the group consisting of a glycol ether, a glycol acetate, a glycol, a pyrrolidone and mixtures thereof, and a polymer solubilizer.

Non-DMSO stripper for advance package metal plating process

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Jhubei, Taiwan

Ming-Da Cheng