Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Da Cheng

Chung-Shi Liu

Wei-Hung Lin

Chih-Wei Lin

Wen-Hsiung Lu

Chen-Hua Douglas Yu

Meng-Tse Chen

Hsiu-Jen Lin

Hui-Min Huang

Kuei-Wei Huang

Mirng-Ji Lii

Wei-Yu Chen

Chun-Cheng Lin

Ching-Hua Hsieh

Chih-Fan Huang

Chen-Shien Chen

Yu-Peng Tsai

Hsien-Wei Chen

Cheng-Ting Chen

Hsuan-Ting Kuo

Ai-Tee Ang

Yu-Hsiang Hu

Ching-Wen Hsiao

Po-Hao Tsai

Tsung-Yuan Yu

Shing-Chao Chen

Hung-Jui Kuo

Bor-Ping Jang

Hao-Yi Tsai

Tin-Hao Kuo

Chih-Hua Chen

Chien Ling Hwang

Chun-Hung Lin

Yu-Feng Chen

Yi-Wen Wu

Chih-Chiang Tsao

Tsung-Ding Wang

Ming-Che Ho

Hao-Jan Pei

Hong-Seng Shue

Han-Ping Pu

Ming-Chih Yew

Yu-Chih Huang

Yeong-Jyh Lin

Tsung-Hsien Chiang

Chia-Lun Chang

Chang-Chia Huang

Sheng-Hsiang Chiu

Sheng-Feng Weng

Kai-Chiang Wu

Chien-Hsun Lee

Chen-Cheng Kuo

Tsung-Shu Lin

Sheng-Yu Wu

Chih-Hsuan Tai

Chien-Hsiun Lee

Cheng-Chung Lin

Yu-Chih Liu

Chien-Wei Lee

Chia-Wei Tu

Hung-Jen Lin

Ting-Ting Kuo

Ching-Yu Chang

An-Jhih Su

Kuo-Chung Yee

Chih-Hang Tung

Chun-Hung Chen

Chin-Yu Ku

Kuo-Ching Hsu

Sey-Ping Sun

Yu-min Liang

Chun-Hui Yu

Yi-Jen Lai

Wei Sen Chang

Yang-Che Chen

Jiun Yi Wu

Yi-Li Hsiao

Jung Wei Cheng

Yu-Min Liang

Ming-Hui Weng

Kuo-Lung Pan

Chia-Shen Cheng

Song-Bor Lee

Ming-Fa Chen

Der-Chyang Yeh

Sung-Feng Yeh

Jui-Pin Hung

Chao-Wen Shih

Cheng-Lin Huang

Hui-Jung Tsai

Chin-Fu Kao

Yao-Chun Chuang

Tzu-Yang Lin

Chita Chuang

Chen-Yu Liu

Chih-Hsien Lin

Wei-Li Huang

Meng-Wei Chou

Ching-Wen Chen

Kuang-Chun Lee

In a method of manufacturing a semiconductor device first conductive layers are formed over a substrate. A first photoresist layer is formed over the first conductive layers. The first conductive layers are etched by using the first photoresist layer as an etching mask, to form an island pattern of the first conductive layers separated from a bus bar pattern of the first conductive layers by a ring shape groove. A connection pattern is formed to connect the island pattern and the bus bar pattern. A second photoresist layer is formed over the first conductive layers and the connection pattern. The second photoresist layer includes an opening over the island pattern. Second conductive layers are formed on the island pattern in the opening. The second photoresist layer is removed, and the connection pattern is removed, thereby forming a bump structure.

Bump structure and method of making the same

A package structure includes a semiconductor device, a molding compound, a first dielectric layer, and a through-via. The molding compound is in contact with a sidewall of the semiconductor device. The first dielectric layer is over the molding compound and the semiconductor device. The through-via is in the molding compound and the first dielectric layer. The through-via is a continuous element and in contact with the first dielectric layer.

Package structure

A method of forming a semiconductor device includes: forming a passivation layer over a conductive pad that is disposed over a substrate; and forming an inductive component over the passivation layer, including: forming a first insulation layer and a first magnetic layer successively over the passivation layer; forming a first polymer layer over the first magnetic layer; forming a first conductive feature over the first polymer layer; forming a second polymer layer over the first polymer layer and the first conductive feature; patterning the second polymer layer, where after the patterning, a first sidewall of the second polymer layer includes multiple segments, where an extension of a first segment of the multiple segments intersects the second polymer layer; and after patterning the second polymer layer, forming a second insulation layer and a second magnetic layer successively over the second polymer layer.

Semiconductor device with inductive component and method of forming

A chip structure is provided. The chip structure includes a substrate. The chip structure includes a first conductive line over the substrate. The chip structure includes an insulating layer over the substrate and the first conductive line. The chip structure includes a conductive pillar over and passing through the insulating layer. The conductive pillar is formed in one piece, the conductive pillar is in direct contact with the first conductive line, and a first sidewall of the first conductive line extends across a second sidewall of the conductive pillar in a top view of the first conductive line and the conductive pillar. The chip structure includes a solder bump on the conductive pillar. The solder bump is in direct contact with the conductive pillar.

Chip structure with conductive pillar and method for forming the same

A semiconductor device structure is provided. The semiconductor device structure includes a semiconductor substrate and a first conductive structure over the semiconductor substrate. The first conductive structure has a first protruding portion extending towards the semiconductor substrate from a lower surface of the first conductive structure. The semiconductor device structure also includes a second conductive structure over the semiconductor substrate. The second conductive structure is substantially as wide as the first conductive structure, and the second conductive structure has a second protruding portion extending towards the semiconductor substrate from a lower surface of the second conductive structure. The first conductive structure is closer to a center point of the semiconductor substrate than the second conductive structure. The second protruding portion is wider than the first protruding portion, and bottoms of the first protruding portion and the second protruding portion are substantially level with each other.

Semiconductor device structure with conductive bumps

A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

Semiconductor package system and method

A semiconductor die including mechanical-stress-resistant bump structures is provided. The semiconductor die includes dielectric material layers embedding metal interconnect structures, a connection pad-and-via structure, and a bump structure including a bump via portion and a bonding bump portion. The entirety of a bottom surface of the bump via portion is located within an area of a horizontal top surface of a pad portion of the connection pad-and-via structure.

Semiconductor die including stress-resistant bonding structures and methods of forming the same

A method for forming a semiconductor structure is provided. The method includes forming a patterned photoresist layer over a substrate and removing the patterned photoresist layer using a photoresist stripping composition that is free of dimethyl sulfoxide. The photoresist stripping composition includes an organic alkaline compound including at least one of a primary amine, secondary amine, a tertiary amine or a quaternary ammonium hydroxide or a salt thereof, an organic solvent selected from the group consisting of a glycol ether, a glycol acetate, a glycol, a pyrrolidone and mixtures thereof, and a polymer solubilizer.

Non-DMSO stripper for advance package metal plating process

In an embodiment, a device includes: a passivation layer on a semiconductor substrate; a first redistribution line on and extending along the passivation layer; a second redistribution line on and extending along the passivation layer; a first dielectric layer on the first redistribution line, the second redistribution line, and the passivation layer; and an under bump metallization having a bump portion and a first via portion, the bump portion disposed on and extending along the first dielectric layer, the bump portion overlapping the first redistribution line and the second redistribution line, the first via portion extending through the first dielectric layer to be physically and electrically coupled to the first redistribution line.

Semiconductor device and method

In an embodiment, a device includes: a dielectric layer over an active surface of a semiconductor substrate; a conductive via in the dielectric layer, the conductive via including a first copper layer having a non-uniform grain orientation; and a bonding pad over the conductive via and in the dielectric layer, the bonding pad including a second copper layer having a uniform grain orientation, a top surface of the bonding pad being coplanar with a top surface of the dielectric layer.

Die bonding pads and methods of forming the same

Some devices included a substrate; and a through via, including a plurality of scallops adjacent the through via in a first region and a plurality of scallops adjacent the through via in a second region, the plurality of scallops having a first depth, the scallops having a greater depth. Some devices include an opening extending into a substrate, including a first region and a second region. Sidewalls of the opening include a stack of first concave portions extending a first distance into the first substrate, and a stack of second concave portions extending a second distance, greater than and parallel to the first distance, into the first substrate. A conductor partially fills the first concave portions and at least partially fills the respective second concave portions.

According to an exemplary embodiment, a substrate having a first area and a second area is provided. The substrate includes a plurality of pads. Each of the pads has a pad size. The pad size in the first area is larger than the pad size in the second area.

Substrate and package structure

A semiconductor device includes a substrate, an interconnect structure, and conductive vias. The substrate has a first side, a second side and a sidewall connecting the first side and the second side, wherein the sidewall includes a first planar sidewall of a first portion of the substrate, a second planar sidewall of a second portion of the substrate and a curved sidewall of a third portion of the substrate, where the first planar sidewall is connected to the second planar sidewall through the curved sidewall. The interconnect structure is located on the first side of the substrate, where a sidewall of the interconnect structure is offset from the second planar sidewall. The conductive vias are located on the interconnect structure, where the interconnect structure is located between the conductive vias and the substrate.

Semiconductor device, semiconductor package, and methods of manufacturing the same

A semiconductor package includes a conductive pillar and a solder. The conductive pillar has a first sidewall and a second sidewall opposite to the first sidewall, wherein a height of the first sidewall is greater than a height of the second sidewall. The solder is disposed on and in direct contact with the conductive pillar, wherein the solder is hanging over the first sidewall and the second sidewall of conductive pillar.

Semiconductor packages having conductive pillars with inclined surfaces

A method includes depositing a first passivation layer over a conductive feature, wherein the first passivation layer has a first dielectric constant, forming a capacitor over the first passivation layer, and depositing a second passivation layer over the capacitor, wherein the second passivation layer has a second dielectric constant greater than the first dielectric constant. The method further includes forming a redistribution line over and electrically connecting to the capacitor, depositing a third passivation layer over the redistribution line, and forming an Under-Bump-Metallurgy (UBM) penetrating through the third passivation layer to electrically connect to the redistribution line.

Capacitor between two passivation layers with different etching rates

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Jhubei, Taiwan

Ming-Da Cheng