Taiwan Semiconductor Manufacturing Comp. Ltd.

Macronix International Co., Ltd.

Ming-Chung Liang

Chien-Chih Chiu

Chia-Ying Lee

Kuan-Wei Huang

Shin-Yi Tsai

Chih-Hao Chen

Hsin-Yi Tsai

Wen-Kuo Hsieh

Chien-Han Chen

Chun-Te Ho

Henry Wei-Ming Chung

Tsung-Hung Chu

Keng-Chu Lin

Jyu-Horng Shieh

Chun-Hung Lee

Chii-Ping Chen

Yu-Yu Chen

Chia-Cheng Chou

Henry Chung

Tzu-Li Lee

Syun-Ming Jang Jang

Erh-Kun Lai

Tsang-Jiuh Wu

Liang-Guang Chen

Chi-Ming Tsai

Wen-Yen Chen

Yuh-Jier Mii

Chien-Wei Chen

Fu-Ming Huang

Shu-Huei Suen

Da-Wei Lin

Chia-Chi Chung

Han-Hsin Kuo

Hsu-Sheng Yu

Jiun-Ren Lai

Lai Chien Wen

Shih-Yu Chang

An-Chi Wei

Kuo-Liang Wei

Jerry Lai

Shiuh-Sheng Yu

Chung Tai Chen

Marowen Ng

Chai-Chi Chung

Stefan Tsai

Hao-Jen Liao

An embodiment includes a method. The method includes: forming a first conductive line over a substrate; depositing a first dielectric layer over the first conductive line; depositing a second dielectric layer over the first dielectric layer, the second dielectric layer including a different dielectric material than the first dielectric layer; patterning a via opening in the first dielectric layer and the second dielectric layer, where the first dielectric layer is patterned using first etching process parameters, and the second dielectric layer is patterned using the first etching process parameters; patterning a trench opening in the second dielectric layer; depositing a diffusion barrier layer over a bottom and along sidewalls of the via opening, and over a bottom and along sidewalls of the trench opening; and filling the via opening and the trench opening with a conductive material.

Interconnect structure with vias extending through multiple dielectric layers

A method of forming a semiconductor device includes forming a conductive line over a substrate; forming an etch stop layer (ESL) over the conductive line, the ESL extending continuously along an upper surface of the conductive line and along an upper surface of a first dielectric layer adjacent to the conductive line, where a first lower surface of the ESL contacts the upper surface of the conductive line, and a second lower surface of the ESL contacts the upper surface of the first dielectric layer, the first lower surface being closer to the substrate than the second lower surface; forming a second dielectric layer over the ESL; forming an opening in the second dielectric layer, the opening exposing a first portion of the ESL; removing the first portion of the ESL to expose the conductive line; and filling the opening with an electrically conductive material to form a via.

Semiconductor device with self-aligned vias

The present disclosure, in some embodiments, relates to a method of performing an etch process. The method is performed by forming a first plurality of openings defined by first sidewalls of a mask disposed over a substrate. A cut layer is between two of the first plurality of openings. A spacer is formed onto the first sidewalls of the mask and a second plurality of openings are formed. The second plurality of openings are defined by second sidewalls of the mask and are separated by the spacer. The substrate is etched according to the mask and the spacer.

Cut first self-aligned litho-etch patterning

The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material over an underlying layer. The spacer material has sidewalls defining a first trench. A cut material is formed over the spacer material and within the first trench. The cut material separates the trench into a pair of trench segments having ends separated by the cut material. The underlying layer is patterned according to the spacer material and the cut material.

Cut last self-aligned litho-etch patterning

A method includes exposing and developing a negative photo resist, and performing a treatment on the negative photo resist using an electron beam. After the treatment, a layer underlying the photo resist is etched using the negative photo resist as an etching mask.

Curing photo resist for improving etching selectivity

The present disclosure relates to a method of performing a semiconductor fabrication process. The method may be performed by forming a spacer material having vertically extending segments along sidewalls of a masking layer and a horizontally extending segment connecting the vertically extending segments. A cut material is formed over a part of the horizontally extending segment, and the horizontally extending segment of the spacer material not covered by the cut material is removed. A layer under the masking layer is patterned according to the masking layer and the spacer material.

Interconnect structure and method

Examples of fabricating an integrated circuit device are disclosed herein. In an embodiment, an integrated circuit workpiece is received that includes a conductive interconnect feature. A first Inter-Level Dielectric (ILD) layer is formed on the conductive interconnect feature, and a second ILD layer is formed on the first ILD layer. A hard mask is formed on the second ILD layer. A via recess is etched extending through the first ILD layer, the second ILD layer and the hard mask to expose the conductive interconnect feature. The etching includes providing a passivation agent that reacts with a material of the hard mask to reduce etchant sensitivity.

Integrated circuit fabrication with a passivation agent

An interconnect structure and a method of forming an interconnect structure are disclosed. The interconnect structure includes a low-k (LK) dielectric layer over a substrate; a first conductive feature in the LK dielectric layer, wherein the first conductive feature has a first sidewall, a second sidewall facing the first sidewall, and a first bottom surface contacting the LK dielectric layer; a first dielectric feature along an upper portion of the first sidewall, wherein a length of the first dielectric feature is at least 10 percent less than a length of the first sidewall; and a second dielectric feature along an upper portion of the second sidewall. The interconnect structure may also include a second conductive feature adjacent to the first conductive feature in the LK dielectric layer.

Interconnect structure and method of forming the same

A semiconductor device and a method of forming the same are provided. An embodiment comprises a target layer and masking layers over the target layer. First openings are formed in the uppermost layer of the masking layers. Spacers are formed along sidewalls of the first openings, remaining first openings having a first pattern. Second openings are formed in the uppermost layer of the masking layers, the second openings having a second pattern. The first pattern and the second pattern are partially transferred to the target layer.

Self-aligned double patterning

In a pattern forming method, a stacked structure, including a bottom layer, a middle layer and a first mask layer, is formed. The middle layer includes a first cap layer, an intermediate layer and a second cap layer. The first mask layer is patterned by using a first resist pattern as an etching mask. The second cap layer is patterned by using the patterned first mask layer as an etching mask. A second mask layer is formed over the patterned second cap layer, and is patterned by using a second resist pattern as an etching mask. The second cap layer is patterned by using the patterned second mask layer as an etching mask. The intermediate layer and the first cap layer are patterned by using the patterned second cap layer as an etching mask. The bottom layer is patterned by using the patterned first cap layer as an etching mask.

Method for manufacturing a semiconductor device

The present disclosure relates to an integrated chip formed by a self-aligned litho-etch process. In some embodiments, the integrated chip has a first plurality of shapes of an integrated chip layer arranged along a first direction at a first pitch. The first plurality of shapes include a first two shapes separated by a first end-to-end space along a second direction perpendicular to the first direction. A second plurality of shapes of the integrated chip layer are arranged along the first direction at a second pitch. The second plurality of shapes include a second two shapes separated by a second end-to-end space along the second direction. A ratio of the first end-to-end space to the second end-to-end space is approximately equal to 2.5:1.

Growing community of inventors

Hsin-Chu, Taiwan

Ming-Chung Liang