Winbond Electronics Corporation

Ming-Chung Chiang

Min-Chieh Yang

Chung-Ming Chu

Wen-Yueh Jang

Bor-Ru Sheu

Wen-Chung Liu

Jong-Bor Wang

Li-Ting Wang

Pai-Hsuan Sun

Bor-Bu Sheu

Provided is a word-line structure including a substrate, a word line, and an epitaxial pattern. The word line is embedded in the substrate. The word line includes a conductive layer, a barrier layer, an insulating layer, and a gate dielectric layer. The barrier wraps a lower portion of the conductive layer. The insulating layer wraps an upper portion of the conductive layer. The gate dielectric layer surrounds the insulating layer and the barrier layer to electrically isolate the barrier layer from the substrate. The epitaxial pattern is disposed between the insulating layer and the substrate and in contact with the substrate. A memory device including the word-line structure and a method of manufacturing the same are also provided.

Word-line structure, memory device and method of manufacturing the same

A method for manufacturing a semiconductor device is provided. The method includes providing a substrate having a first region and a second region. The method also includes forming an interconnection structure on the first region and a fuse structure on the second region. The method further includes forming a first conductive pad on the interconnection structure. In addition, the method includes forming a capping layer, an etching stop layer and a dielectric layer to cover the first conductive pad and the fuse structure. The method further includes performing an etching process so that a first opening is formed to expose the conductive pad and a second opening is formed directly above the fuse structure. During the etching process, the first dielectric layer has a first etching rate, and the etching stop layer has a second etching rate that is lower than the first etching rate.

Semiconductor devices and methods for manufacturing the same

An interconnect structure including a conductive layer, a spacer, a dielectric layer, and a contact is provided. The conductive layer is disposed on a substrate. The spacer is disposed on a sidewall of the conductive layer. The dielectric layer covers the conductive layer and the spacer. The contact is disposed in the dielectric layer and located on the conductive layer.

Interconnect structure having spacer disposed on sidewall of conductive layer, manufacturing method thereof, and semiconductor structure

Provided is a resistance memory device including a dielectric layer, a conductive layer, a bottom electrode, a top electrode and a variable resistance layer. The dielectric layer is disposed on a substrate and has a first opening constituted by a lower opening and an upper opening. The conductive layer fills up the lower opening. The bottom electrode is disposed on the bottom and on at least a portion of the sidewall of the upper opening. The top electrode is disposed in the upper opening. The variable resistance layer is disposed between the top electrode and the bottom electrode.

Resistance memory device

The memory-storage node of the present invention includes a semiconductor substrate, a first insulating layer over the substrate, a conductive layer formed within the first insulating layer, and a barrier layer formed over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. The memory-storage node further includes a first electrode over the barrier layer, a dielectric layer over the first electrode, and a second electrode over the dielectric layer. The method for fabricating the memory storage-node of the present invention provides a semiconductor substrate and forms a first insulating layer on the substrate. A first opening is formed in the first insulating layer and a conductive layer is provided in the first opening. A barrier layer is then formed in the first opening and over the conductive layer. The barrier layer, preferably contains a ruthenium-based material, is conductively coupled with the conductive layer. A second insulating layer is formed over the first insulating layer and the barrier layer. A second opening is formed in the second insulating layer to expose a portion of the underlying barrier layer. A first electrode is formed in the second opening and a dielectric layer is formed on the second insulating layer and the first electrode. Finally, a second electrode is formed over the dielectric layer.

Memory-storage node and the method of fabricating the same

A method for fabricating semiconductor memory cells such as dynamic random access memory (DRAM) and ferroelectric random access memory (FRAM) with improved contact between the capacitor electrode and the underneath device area. It includes the following main steps of: (1) forming a first dielectric layer on a wafer surface; (2) forming at least one through opening in the first dielectric layer; (3) forming a ruthenium based plug in the through opening; and (4) forming a capacitor in contact with the ruthenium based plug. The ruthenium based plug can be made of ruthenium metal, conductive ruthenium oxide, or a stack of conductive ruthenium oxide and ruthenium metal. The method allows the memory cell to be made without the need for a barrier, which is required to protect the storage electrode from reacting with Si atoms during the fabrication process.

Growing community of inventors

Changhua County, Taiwan

Ming-Chung Chiang