Advanced Micro Devices Corporation

Other

Ming Chun Chen

Paul J Steffan

Yung-Tao Lin

Ying Shiau

Bryan M Tracy

Steven J Zika

Wanyee Apple Chow

A method of determining classification codes for defects occurring in semiconductor processes comparing images of defects from a first selected wafer with images of defects in a first image reference library. The images in the first image reference library are updated from a master image reference library. The images in the master image reference library are the best images of defect types. The images in the master image reference library are in a format readable by all review stations utilized to review the images of the defect.

Method to accurately determine classification codes for defects during semiconductor manufacturing

A method of determining an accurate disposition decision for each inspected layer in a wafer lot wherein a measured defect density is compared to a calculated disposition criterion determined for each inspected layer. If the measured defect density is above the calculated disposition criterion the wafer lot is placed on hold and if the measured defect density is at or below the calculated disposition criterion the wafer lot is sent to the next process. The disposition criterion for each layer is determined from a yield value determined for each layer. The yield value is the yield necessary for each layer to obtain a profitable product and is determined from cost data for each die in the wafer lot and a risk factor determined by management and includes market data such as selling price and demand for the product. The yield value is combined with defect sensitivity determined for each layer. The defect sensitivity is determined from the combination of critical area and historical frequency for each layer.

Critical area cost disposition feedback system

A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test parameters. The set of predicted wafer electrical test parameters are compared with wafer electrical test specifications tabulated for each process during the manufacturing process. During the comparison, it is determined whether the predicted wafer electrical test parameters are within the specifications for the process and circuit simulations are then conducted using the predicted wafer electrical test parameters. Device performance is predicted from the circuit simulations and the disposition of the wafer lot is determined utilizing tabulated from a disposition performance table.

Disposition tool for factory process control

A method of utilizing associated process data parameters in the manufacture of semiconductor wafers by converting tool-based data to lot based data in order to predict wafer electrical test results from measured in-line critical dimensions, lot based data and the converted tool-based data. The converted tool-based data is obtained by interpolating data between a measurement obtained from a tool at a first time and a measurement obtained from the tool at a second time. The data association is obtained using LaPlace-Everett interpolation. The converted tool-based data can also be obtained by extrapolating data from the historical measurements taken from the tool.

System for process data association using LaPlace Everett interpolation

A method of manufacturing semiconductor wafers using a simulation tool to determine a set of predicted wafer electrical test measurements that are compared to a set of target wafer electrical test measurements to obtain a set of optimized process parameters for the equipment for the next process. The optimized process parameters are compared to the equipment characteristics for the equipment of the next process and the process parameters for the next process are automatically adjusted.

Automatic recipe adjust and download based on process control window

A defect management system with a method to update a database with defect data concerning propagator defect data. Defect data obtained from each layer formed on a semiconductor wafer is stored in a relational database. Defect data determined in a current layer to be defect data for a defect observed in a previous layer is defined as data concerning a propagator defect. Propagator defect data is used to update the data in the database relating to the previous layer.

Automatic defect reclassification of known propagator defects

A semiconductor wafer optical scanning system and method for determining defects on a semiconductor wafer is disclosed. The method for determining wafer defects is based on maximum allowable defects on a swath basis, rather than maximum allowable defects on a wafer basis. The method step include determining the scanned area of an individual swath that is based on a recipe set-up, consistent with the capability of the optical scanning equipment being used and the particular semiconductor wafer being tested for defects. The predetermined swath area is supplied and stored in the optical scanning system along with the maximum allowable defect density determined by the user. By using the predetermined maximum allowable defects for a swath as a limit, defect analysis may be performed on the entire wafer. The optical scanning system would stop acquiring defects for the current swath being analyzed whenever the defect limit is reached, or until the swath defect analysis has been completed. The optical scanning would proceed to the next swath determining its defect and continuing in such a manner until the wafer is completely scanned.

Semiconductor wafer optical scanning system and method using swath-area

A method to accurately classify defects on a semiconductor wafer wherein a scanning tool detects defects and assigns values to parameters that are characteristic of each defect. The values of the characteristic parameters represent a thumbprint of each defect and the defects are placed into 'bins' according to the thumbprint of each defect. A sample of defects in each bin is analyzed and assigned a classification code.

Intelligent usage of first pass defect data for improved statistical

A method of obtaining accurate actual ion implantation equipment used in ion implantation processes during the manufacture of semiconductor devices. A monitor structure for each ion implant process is implanted with ions during the ion implant process. A control monitor structure is implanted with boron ions. The concentration profiles of all implanted monitor structure are determined during wafer electrical tests (WET). The as-implanted concentration profile is determined for the boron-implanted control monitor structure and the thermal budget of the manufacturing process is determined. The as-implanted concentration profiles of the remaining monitor structures are determined using the thermal budget determined from the boron-implanted control monitor structure. The actual operating parameters of the ion implantation equipment is determined from the as-implanted concentration profiles.

Ion implantation feedback monitor using reverse process simulation tool

A method of determining classification codes for defects occurring in semiconductor manufacturing processes and for storing the information used to determine the classification codes. A wafer is selected from a production lot after the lot is sent through a first manufacturing process. The selected wafer is scanned to determine if there are defects on the wafer. Images of selected defects are examined and a numerical value is assigned to each of N elemental descriptor terms describing each defect. A classification code is determined for each defect based upon the numerical values assigned to the N elemental descriptor terms. The classification code and numerical values assigned to the N elemental descriptor terms are stored in a database. The wafer is sent through each sequential process and classification codes are assigned to additional defects selected after each sequential process. The classification codes and numerical values assigned to the N elemental descriptor terms for the additional selected defects are stored in the database. The stored numerical values assigned to the N elemental descriptor terms to modify the classification code. All of the defects stored in the database are assigned new classification codes in accordance with the modified classification code. A new classification code can be generated and all of the stored defects are assigned new classification codes in accordance with the new database.

Automatic defect classification (ADC) reclassification engine

A defect management system with a method to identify and reclassify previously classified propagator defects. The defect management system also has a method of identifying cluster defects and selecting at least one cluster defect to classify.

Intelligent adc reclassification of previously classified propagator

Defect scanner sensitivity and accuracy are improved for light scattering defect scanners and pattern matching defect scanners by calibrating the defect scanners to each die on a wafer using preset marks on the corresponding die. The marks have a predetermined size based on the sensitivity of the defect scanners and a predetermined position relative to the circuit pattern on the corresponding die. Alignment of the defect scanners to a specific die provides improvement in coordinate accuracy over alignment with respect to an entire wafer. A layout mapping defect filtering system collects defect scan data and determines the interaction between the detected defects and a circuit layout. The layout mapping defect filtering system provides automatic identification in real time of killer defects that cause failure of the completed integrated circuit, and classifies and analyzes defects to identify potential killer defects within specified defect classes to identify defective die. The system provides accurate yield estimation to determine whether a produced wafer should be scrapped, and also provides accumulated data for yield improvement studies including quality control and circuit redesign.

Arrangement for improving defect scanner sensitivity and scanning

A vehicle communications system having a remote control unit installed in the interior of a vehicle and a display unit located on the exterior of the vehicle. The display unit has an input from the remote control unit and an input from a vehicle interface module that has inputs from the vehicle such as the braking system and the turning signal system. The remote control unit is controllable by the driver in the vehicle and has a table of preset and preprogrammed messages selectable by the driver. The driver selects a message to be displayed and sends the message to the display unit. Any input to the vehicle interface module from the vehicle signaling systems overrides the signal input from the remote control unit unless the display unit is mounted on the front of the vehicle. The driver can select a message from a table of messages that are sequentially displayed on the remote control unit. The table of messages is stored on a flash memory in the remote unit and in a flash memory in the display unit. The table of messages in the remote unit is programmable via a USB programming port. The table of messages in the display unit can be programmed via an RF signal sent to the display unit by the remote unit.

Vehicle communication device

An apparatus and method for selecting products to inspect for defects performs in-situ monitoring of a processing tool during a manufacturing processing step. The data from the in-situ monitoring for a test run of products is correlated by a neural network with data collected during inspection of the test products for defects. During a production run of products, the in-situ monitor data is provided to the neural network which, based on the input data and the correlation, predicts the values of the data that would be collected upon inspection of the products. Specific products from the production run are selected for inspection based upon the predicted values.

Method and apparatus for inspecting manufactured products for defects in

A method of manufacturing semiconductor wafers using a simulation tool to determine predicted wafer electrical test measurements. The simulation tool combines in-line critical dimensions from previous from previous processes run on the current wafer lot, data from previous lots for processes subsequent to the process being run on the current lot and calibration simulation data obtained from the comparison of the predicted wafer electrical test measurements and collected wafer electrical test measurements taken from previous actual wafer electrical test measurements.

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Milpitas, CA, United States of America

Ming Chun Chen