Realtek Semiconductor Inc.

Ming-Chun Chang

Yi-Shu Chang

Cheng-Shun Liao

Chi-Kung Kuan

Zou-Ping Chen

Wen-Shiung Weng

Ming-Jane Hsieh

Tung-Chen Kuo

Chia-Pei Chang

Sheng-Kai Chen

Kuo-Lin Tai

A visual effect generating module for changing visual effects of a selected image block within an image area is disclosed. The visual effect generating module includes a color changing module for receiving and changing pixel values of a plurality of pixels within the selected image block and a first multiplexer coupled to the color changing module for selectively outputting pixels corresponding to the image area or pixels output from the color changing module.

Method and apparatus for generating visual effects

A method for recording a plurality of graphic objects is disclosed. Each graphic object includes at least one common parameter and at least one object data. The method includes recording the at least one common parameter corresponding to the plurality of graphic objects in a common parameter section; and respectively recording the at least one object data of the plurality of graphic objects in corresponding object sections; wherein the at least one common parameter and the at least one object data are utilized to describe characteristics of the graphic objects.

Method of recording a plurality of graphic objects and processing apparatus thereof

A video processing apparatus includes: a line-based data encoder for performing line-based data encoding on an input signal to generate a line-based data encoded signal; and a video signal controller coupled to the line-based data encoder for receiving a first video signal and the line-based data encoded signal, decoding the line-based data encoded signal to generate a second video signal, and choosing one of the first and second video signals to generate an output signal.

Video processing apparatus and method thereof

A delaying stage selecting circuit for selecting a specific delaying stage from a plurality of delaying stages, where the delaying stages are for outputting delayed clock signals, includes: a first register for sampling the delayed clock signals according to a clock signal to generate sampled values; first memory units, wherein the first memory units are utilized to memorize the sampled values, and each of first memory unit outputs at least one of the sampled values according to a corresponding first selecting signal; a first selecting unit, for outputting the sampled values according to a second selecting signal; a determining module, for determining if the sampled values meet a specific relation, where if the determination result is positive then determining the particular delaying stage; and a counter for generating a counting value to control the delayed clock signal sampled by the first register.

Delaying stage selecting circuit and method thereof

A clock tuning device and method for executing overclocking operations on plural elements disposed on a motherboard. The clock tuning device includes a phase-locked loop for outputting a plurality of clock signals to the elements, and a control circuit for controlling the phase-locked loop to adjust the frequencies of the clock signals, so as to execute the overclocking operations on the elements, respectively. The method includes the steps of: increasing the frequency of a first clock signal until one of the elements can't work normally due to an utmost frequency of the first clock signal; resetting all the elements and operating the element corresponding to the first signal according to a safe frequency of the first clock signal; and repeating the above steps to perform overclocking operation on each of the other elements.

Clock generating device and method for executing overclocking operation

A signal generator for generating a clock with lower jitter. The signal generator includes a multi-phase clock generator for generating a plurality of multi-phase reference clocks with same frequency, a multiplexer for selecting one reference clock as an output clock according to a phase selecting signal, a phase-swallow control unit having a comparator for comparing a swallow value with a reference value out of order and outputting the comparing result as a swallow control signal, and a clock selector for receiving the swallow control signal and generating the phase selecting signal. Because the reference value is provided by a counter in bit-reversed, the swallow control signal is dispersed smoothly and the jitter of the output clock is reduced.

Growing community of inventors

Chia-I, Taiwan

Ming-Chun Chang