Rambus Inc.

Osram Sylvania Inc.

Avanex Corporation

Novellus Systems Incorporated

Ledvance Gmbh

Other

Personalis, Inc.

Lam Research Corporation

Oclaro (north America Inc.)

Cryptography Research, Inc.

Photonedge, Inc.

Ming Chu Li

Song Peng

Scott C Best

Donald R Mullen

Giovanni Barbarossa

Bart Jan Van Schravendijk

John West

Mark R Pratt

Richard Chen

Keng Chen

Robert Reed Harrison

Jason Harris

Yuhao Liu

Mandyam Sriram

Hu Kang

Tom Mountsier

Nilesh Patel

Yi Yang

Jon Henri

Gary Bela Bronner

Arunava Dutta

Adrien LaVoie

Qi Dai

Anne Janet Milliez

Frederick Abbott Ware

Kevin S Donnelly

Dennis Michael Hausmann

Shankar Swaminathan

Anil Jeswani

Ramesh Chandrasekharan

Kevin J Ilcisin

Easwar Srinivasan

Thomas W Mountsier

Mohamed Sabri

James Samuel Sims

Sirish K Reddy

Joseph Allen Olsen

Qiong Huang

Damien Martin Slevin

Curtis Warren Bailey

Ravidasa Hegde

Arnulf Rupp

Philip Rioux

Jason L Tian

Arul N Dhas

Nitin Juneja

Antonio Xavier

Chiu Chi

William Z Guan

Shahram Nikoukary

Jonghyun Cho

Thomas G Jewell

Di Yang

Tom Dorsh

Julian Hsieh

Xingzhong Zhao

Bryan Schlief

Xiaojun Wang

Vidisha Gupta

Brad Laird

Saangrut Sangplug

Belgacem Haba

Adrien Lavoie

Thomas J Giovannini

Abhijit Mukun Abhyankar

John Bondo Hansen

David A Secker

Dongyun Lee

Mark Evan Marson

M Ziaul Karim

Ravindranath T Kollipara

Akhil N Singhal

Ronald Roberts

Andrew Johnsen

Steven C Allen

Renaud Richard

Sayeh Khalili

Arun Vaidyanath

Douglas Harriott

Ahmed Eissa

Philip E Moskowitz

Tianzheng Jiang

Peng Xiao

Sarah Bazydola

Haijun Yuan

Bart K Van Schravendijk

Camil-Daniel Ghiu

Napoli Oza

Marshall Stowell

Kareem Boumatar

Frank Wu

Tina Moller Tagmose

Christopher M Bartlett

Chander Radhakrishnan

Benson Q Tong

Kerry J Denvir

Mohammed Sabri

Joseph Bradley Laird

Jian Xu

M Zlaul Karim

An apparatus for providing plasma processing is provided. A plasma processing chamber is provided. A first turbopump with an inlet is in fluid connection with the plasma processing chamber and an exhaust. A gas source provides gas to the plasma processing chamber. At least one gas line is in fluid connection between the gas source and the plasma processing chamber. At least one bleed line is in fluid connection with the at least one gas line. At least one gas line valve is on the at least one gas line located between, where the at least one bleed line is connected to the at least one gas line and the plasma processing chamber. At least one bypass valve is on the at least one bleed line.

Method and apparatus for processing wafers

Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address—C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

Packaged integrated device with memory buffer integrated circuit die and memory devices on module substrate

A memory is disclosed that includes a logic die having first and second memory interface circuits. A first memory die is stacked with the logic die, and includes first and second memory arrays. The first memory array couples to the first memory interface circuit. The second memory array couples to the second interface circuit. A second memory die is stacked with the logic die and the first memory die. The second memory die includes third and fourth memory arrays. The third memory array couples to the first memory interface circuit. The fourth memory array couples to the second memory interface circuit. Accesses to the first and third memory arrays are carried out independently from accesses to the second and fourth memory arrays.

Multi-die memory device

A computer-implemented method for processing and/or analyzing nucleic acid sequencing data comprises receiving a first data input and a second data input. The first data input comprises untargeted sequencing data generated from a first nucleic acid sample obtained from a subject. The second data input comprises target-specific sequencing data generated from a second nucleic acid sample obtained from the subject. Next, with the aid of a computer processor, the first data input and the second data input are combined to produce a combined data set. Next, an output derived from the combined data set is generated. The output is indicative of the presence or absence of one or more polymorphisms of the first nucleic acid sample and/or the second nucleic acid sample.

Methods and systems for genomic analysis

A light structure including a first housing having a light engine including at least one lighting scheme comprised of LEDs; and a second housing for containing driver electronics. The driver electronics including at least a mixing integrated circuit (IC) for controlling current to the at least one lighting scheme, and a near field communication (NFC) circuit having a near field communication (NFC) receiver and memory for storing instructions for sending pulse width modulation (PWM) signals from the NFC circuit to the mixing integrated circuit. The NFC receiver can receive an external command signal that the instructions stored in the memory of the NFC circuit employ to provide for an NFC control signal including at least one of the PWM signals to the mixing integrated circuit (IC). The mixing integrated circuit (IC) receiving the control signal sets current to control light characteristics for light being emitted by the light engine.

Driver electronics for light emitting diode light engine with integrated near field communication based controls

Disclosed is an integrated circuit die of a memory buffer integrated circuit that is placed aggregately closer to the solder balls that connect to the input (i.e., host command/address&#x2014;C/A) signals than the output solder balls (i.e., memory device C/A) signals. This decreases the length of the host C/A signals from the memory controller to the memory buffer device when the memory module is placed in a system.

Packaged integrated device having memory buffer integrated circuit asymmetrically positioned on substrate

Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a semiconductor device is disclosed. The semiconductor device includes a first semiconductor die having a first bonding surface that is formed with a first set of contacts patterned with a first connection pitch. A second semiconductor die has a second bonding surface that is formed with a second set of contacts patterned with a second connection pitch. The second set of contacts are further patterned with a paired offset. The second semiconductor die is bonded to the first semiconductor die such that the first set of contacts is disposed in opposed electrical engagement with at least a portion of the second set of contacts.

Method and apparatus to improve connection pitch in die-to-wafer bonding

The present disclosure provides methods and structures for controlling characteristics of light being projected from a light source. In one embodiment, the method includes selecting a color setting of light to be projected by a light engine having at least one light emitting diode; and monitoring temperature of the light engine with a thermistor. The changes in resistance measurements taken from the thermistor are correlated to changes in the temperature of the light engine. The method for controlling characteristics of light being projected from the light source may further include setting characteristics of the electrical signal to energize the light emitting diodes of the light engine to provide the color setting selected at the temperature of the light engine measured using the thermistor.

Light emitting diode luminaires with temperature feedback

The embodiments herein are directed to technologies for backside security meshes of semiconductor packages. One package includes a substrate having a first interconnect terminal of a first type and a second interconnect terminal of a second type. The package also includes a first security mesh structure disposed on a first side of an integrated circuit die and a conductive path coupled between the first interconnect terminal and the second interconnect terminal. The first security mesh structure is coupled to the first interconnect terminal and the second interconnect terminal being coupled to a terminal on a second side of the integrated circuit die.

Packaging techniques for backside mesh connectivity

An anti-tamper layer is applied to a blank wafer. The layered wafer is then diced into shield dies. A shield die is oxide-to-oxide bonded to the top of an active die such that removing the shield die will damage the active die. The shield die may be sized and positioned such that wirebond pads along one or more edges of the active die remain exposed. The exposed wirebond pads may be used to electrically connect, via wirebonds, the active die to a substrate. A second shield die may be attached to the bottom of the active die to help protect against the use of bottom-to-top delayering.

Integrated circuit shield

A driver circuit that includes an input side including a power input circuit and an output side including a light emitting diode (LED) output current circuit. The output side of the driver circuit includes an output smoothing capacitor for controlling flicker percentage. A light emitting diode (LED) power supply circuit is present between the input side and the output side for controlling current from the AC power input circuit to the light emitting diode (LED) output current circuit. The LED power supply circuit includes at least two linear current regulators that are connected in parallel. The circuit also includes a controller circuit including a controller for signaling the light emitting diode (LED) power supply to control current to the light emitting diode (LED) output current circuit to provide a lighting characteristic.

Low standby power smart bulb based on a linear power supply

A driver circuit for lighting applications that includes a power input circuit for receiving power; a light emitting diode (LED) output current circuit for interfacing with a light source; and a light emitting diode (LED) power supply circuit for controlling current to the light emitting diode (LED) output current circuit. A controller circuit is present in the circuit for signaling the light emitting power supply (LED) to control current to the light emitting diode (LED) output current circuit. The controller is reset by removing power to the controller. A smoothing capacitor is present for stabilizing at least an output voltage. The circuit further includes a current rectifying circuit that prohibits back current traveling from the smoothing capacitor to the controller circuit when the AC power is off.

Reliability of hardware reset process for smart light emitting diode (LED) bulbs

Growing community of inventors

Chandler, AZ, United States of America

Ming Chu Li