Macronix International Co., Ltd.

Asustek Computer Inc.

Siliconware Precision Industries Co., Ltd.

Ememory Technology Inc.

Ming-Chih Hsieh

Nai-Ping Kuo

Kuen-Long Chang

Chun-Hsiung Hung

Ken-Hui Chen

Su-Chueh Lo

Han-Sung Chen

Wen-Pin Tsai

Lian-Tien Ke

Ming-Fang Hsu

Chien-Ping Huang

Chi-Chuan Wu

Chien-Hung Ho

Jui-Yu Chuang

Hong-Chin Lin

Jain-Hao Lu

Lien-Chih Chan

A data receiving stage circuit of a memory circuit receives a serial input signal and a chip enable signal. A data writing circuit of the memory circuit generates at least one of a command signal and a data signal according to the serial input signal. A power supply circuit of the memory circuit generates an operating voltage for a memory cell array to perform a data access operation. A data output stage circuit of the memory circuit outputs a readout data. A controller of the memory circuit performs a switching operation of an operating state of the memory circuit according to a change of the chip enable signal. The controller determines a disable or enable state of the data receiving stage circuit, the data writing circuit, the power supply circuit, and the data output stage circuit according to the operating state.

Memory circuit

A memory device includes a memory array and a logic unit communicatively coupled to the memory array. The memory array includes a plurality of pages for storing array data and a plurality of extra arrays respectively corresponding to the plurality of pages for storing extra data. The logic unit is configured to receive a read instruction, and perform a read operation in a first access mode or in a second access mode. In the first access mode, the logic unit sequentially reads out the array data stored in the plurality of pages. In the second access mode, the logic unit sequentially reads out the array data stored in the plurality of pages and the extra data stored in the plurality of extra arrays.

Memory device and operating method of same

In the disclosed technology, the device identification code of a memory integrated circuit is changeable. In some cases, multiple device identification codes are stored on the memory integrated circuit, and multiple device identification code selection data are stored on the memory integrated circuit. A device identification code register can store a selected device identification code.

Method and apparatus of changing device identification codes of a memory integrated circuit device

A data protecting method for a memory, which comprising a volatile memory and a non-volatile memory for storing data and data protection information, comprises the following steps. Firstly, load the data protection information to the volatile memory from the non-volatile memory. Next, protect the data stored in the memory according to the data protection information stored in the volatile memory.

Data protecting method capable of effectively recording protection information and memory using thereof

An integrated circuit device includes a pad adapted to receive a signal from an internal or external driver, and an input buffer circuit including an input terminal coupled to the pad. The input buffer circuit includes a pass transistor having a control terminal, a first conduction terminal connected to the pad, and a second conduction terminal connected to a first voltage. The input buffer circuit also includes a latch having a terminal electrically coupled to the control terminal of the pass transistor. The input buffer circuit further includes circuitry coupled to the latch, the circuitry including a feedback transistor having a control terminal electrically coupled to the pad, a first conduction terminal electrically coupled to a second voltage, and a second conduction terminal coupled to the latch.

Apparatus and method to tolerate floating input pin for input buffer

Electronic device

According to an embodiment of the present invention, a method for detecting word line leakage in a memory device includes coupling a first word line in the memory device to a voltage source while coupling a second word line in the memory device to a ground level voltage. Next, the first word line is decoupled from the voltage source. The method also includes comparing a current of the first word line with a predetermined reference current for determining a leakage condition of the word line.

Apparatus and method for detecting word line leakage in memory devices

Some embodiments of the present invention provide a memory device including a first memory array having a first word line and a comparator circuit having a first terminal coupled to a reference voltage and a second terminal coupled to a first switch selectively coupling the first word line to a power source or the second terminal. In an embodiment, the reference voltage is selected for identifying a leakage condition associated with the first word line. In another embodiment, the first switch is configured to couple the first word line to the power source for a first predetermined period of time to allow charging of the first word line. In another embodiment, the first switch is configured to couple the first word line to the second terminal of the comparator for at least a second predetermined period of time.

A method for detecting word line leakage in a memory device includes coupling a first plurality of word lines in the memory device to a voltage source while grounding a second plurality of word lines. Each of the second plurality of word lines is adjacent to a corresponding one of the first plurality of word lines. The method includes waiting for a period of time to allow the word lines to reach a predetermined read voltage level. The method also includes decoupling the first plurality of word lines from the voltage source and waiting for a second predetermined period of time to allow the first plurality of word lines to discharge. The method further includes sensing a current associated with the word lines, and comparing the current with a predetermined reference current which is selected for identifying a word line leakage condition associated with the first plurality of word lines.

A four-phase dual pumping circuit has a number of stages according to the required output voltage based on an input voltage. Each stage has a first pumping unit and a second pumping unit that are mirror and identical to each other and electrically coupled to each other. The dual pumping circuit is controlled by four-phase clocks which are made from one pair of out of phase clocks. The transistors of the dual pumping circuit have special substrate connection to minimize body effects. The four-phase dual pumping circuit uses NMOSFETS for negative pumping and PMOSFETS for positive pumping.

Four-phase dual pumping circuit

A semiconductor package with a heat dissipating structure is proposed, in which the heat dissipating structure is precisely positioned on a substrate, in a manner that a plurality of solder balls self-align with ball pads formed on the substrate, and support a heat sink to be positioned above a semiconductor chip mounted on the substrate. This therefore makes the heat sink closely abut a molding cavity of an encapsulating mold in a molding process, and prevents resin flash from occurring on the heat sink, so that a surface of the heat sink can be directly exposed to the atmosphere for improving heat dissipating efficiency. Moreover, the solder balls characterized in softness deform in response to a pressure generated by the encapsulating mold during molding. Therefore, the substrate can be protected from being damaged by the pressure, and thus quality of the semiconductor package can be assured.

Growing community of inventors

Taipei, Taiwan

Ming-Chih Hsieh