Taiwan Semiconductor Manufacturing Comp. Ltd.

National Yang Ming Chiao Tung University

Ming-Chien Tsai

Hao-I Yang

Atul Katoch

Ching-Wei Wu

Kao-Cheng Lin

Ming-Hung Chang

Chen-Lin Yang

Saman M I Adham

Donald George Mikan, Jr

Tsung-Yung Chang

Uppu Sharath Chandra

Cheng Hung Lee

Chia-En Huang

Chung-Yi Wu

Yu-Hao Hsu

Nan-Chun Lien

Ching-Te Chuang

Shyh-Jye Jou

Wei-Chiang Shih

Yi-Wei Lin

Kuen-Di Lee

Wei Hwang

Chih-Yu Lin

Chia-en Huang

Geng-Cing Lin

Ming-Hsien Tu

Shao-Cheng Wang

Jyun-Kai Chu

An exemplary testing environment can operate in a testing mode of operation to test whether a memory device or other electronic devices communicatively coupled to the memory device operate as expected or unexpectedly as a result of one or more manufacturing faults. The testing mode of operation includes a shift mode of operation, a capture mode of operation, and/or a scan mode of operation. In the shift mode of operation and the scan mode of operation, the exemplary testing environment delivers a serial input sequence of data to the memory device. In the capture mode of operation, the exemplary testing environment delivers a parallel input sequence of data to the memory device. The memory device thereafter passes through the serial input sequence of data or the parallel input sequence of data to provide an output sequence of data in the shift mode of operation or the capture mode of operation or passes through the serial input sequence of data to provide a serial output sequence of scan data in the scan mode of operation.

Scan synchronous-write-through testing architectures for a memory device

A method includes: during a read operation of a first storage node and a second storage node formed by cross-coupled inverters, based on data stored in the first storage node and the second storage node, causing a first auxiliary branch or a second auxiliary branch to assist a corresponding one of the cross-coupled inverters in holding data; and during a write operation of the first storage node and the second storage node, based on data to be written to the first storage node and the second storage node, causing the first auxiliary branch or the second auxiliary branch to assist a corresponding one of the cross-coupled inverters in flipping data.

Method of controlling auxiliary branches for SRAM cell

A memory device includes storage layers each comprising memory cells arranged in a plurality of rows, bit lines coupled to the memory cells in the corresponding rows, tracking cells arranged in at least one row, at least one tracking bit line coupled to the tracking cells, and at least one sense amplifier coupled to the bit lines. The sense amplifier is configured to detect data stored in the memory cells, and has an enabling terminal coupled to the at least one tracking bit line. The memory device further comprises word lines and tracking word lines extending through the storage layers. The word lines are coupled to the corresponding memory cells in the storage layers. The tracking word lines are coupled to the corresponding tracking cells in the storage layers.

Memory device with tracking mechanism

A circuit includes a first inverter, a second inverter, a first auxiliary branch and a second auxiliary branch. The first and second inverters are cross-coupled to form a first storage node and a second storage node. The first auxiliary branch is coupled to the first storage node and configured to assist the first inverter in holding data based on data stored at the second storage node during a read operation, and assist the first inverter in flipping data based on data to be written to the first storage node during a write operation. The second auxiliary branch is coupled to the second storage node and configured to assist the second inverter in holding data based on data stored in the first storage node during the read operation, and assist the second inverter in flipping data based on data to be written to the second storage node during the write operation.

Data-controlled auxiliary branches for SRAM cell

A memory includes a clock generator for providing a first clock signal responsive to a second clock signal and a feedback signal. A feedback loop provides the feedback signal and includes a tracking wordline, a tracking bitline, a tracking bit cell, and a tracking wordline driver for driving the tracking wordline responsive to the first clock signal. The memory includes a tracking wordline level tuner for reducing a voltage level of a tracking wordline signal on the tracking wordline responsive to a weak bit control signal.

Memory device with tracking wordline voltage level circuit and method

The present invention provides an oscillator which is based on a 6T SRAM for measuring the Bias Temperature Instability. The oscillator includes a first control unit, a first inverter, a second control unit, and a second inverter. The first control unit is coupled with the first inverter. The second control unit is coupled with the second inverter. The first control unit and the second control unit is used to control the first inverter and the second inverter being selected, biased, and connected respectively, so that the NBTI and the PBTI of the SRAM can be measured separately, and the real time stability of the SRAM can be monitored immediately.

Oscillato based on a 6T SRAM for measuring the bias temperature instability

A threshold voltage measurement device is disclosed. The device is coupled to a 6T SRAM. The SRAM comprises two inverters each coupled to a FET. Power terminals of one inverter are in a floating state; the drain and source of the FET coupled to the inverter are short-circuited. Two voltage selectors, a resistor, an amplifier and the SRAM are connected in a negative feedback way. Different bias voltages are applied to the SRAM for measuring threshold voltages of two FETs of the other inverter and the FET coupled to the other inverter. The present invention uses a single circuit to measure the threshold voltages of the three FETs without changing the physical structure of the SRAM. Thereby is accelerated the measurement and decreased the cost of the fabrication process and measurement instruments.

Threshold voltage measurement device

Growing community of inventors

Kaohsiung, Taiwan

Ming-Chien Tsai