Phison Electronics Corporation

Elite Semiconductor Memory Technology, Inc

Ming-Chien Huang

Chien-Yi Chang

Chia-Lung Ma

Tzu-Chia Huang

Chien Ho Liao

Yi-Chung Chen

A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.

Signal calibration method, memory storage device, and memory control circuit unit

A circuit layout structure and a memory storage device are disclosed. The circuit layout structure includes a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first data line, a second data line, a first clock enable signal line and a second clock enable signal line. The first data line is configured to access the first volatile memory modules in parallel by a first sequential bit group. The second data line is configured to access the second volatile memory modules in parallel by a second sequential bit group. The first clock enable signal line and the second clock enable signal line are configured to control the first volatile memory modules and the second volatile memory modules to enter a self-refresh mode respectively.

Circuit layout structure for volatile memory modules and memory storage device

A memory interface circuit, a memory storage device and a configuration status checking method are provided. The memory interface circuit is configured to connect a plurality of volatile memory modules and a memory controller. The volatile memory modules include a first volatile memory module and a second volatile memory module. The memory interface circuit includes a first interface circuit and a second interface circuit. The first interface circuit is configured to receive a first signal from the first volatile memory module and transmit a second signal to the second interface circuit through an internal path of the memory interface circuit. The second interface circuit is configured to transmit a third signal to the second volatile memory module according to the second signal to evaluate a configuration status of the memory interface circuit by the third signal.

Memory interface circuit, memory storage device and configuration status checking method

A memory interface circuit, a memory storage device and a signal generation method are provided. The memory interface circuit is configured to connect a volatile memory module and a memory controller. The memory interface circuit includes a clock generation circuit, a first interface circuit and a second interface circuit. The clock generation circuit is configured to provide a reference clock signal. The first interface circuit is configured to provide an address signal to the volatile memory module based on a first transition point of the reference clock signal. The second interface circuit is configured to provide a command signal to the volatile memory module based on a second transition point of the reference clock signal. The first transition point is one of a rising edge and a falling edge of the reference clock signal. The second transition point is the other one of the rising edge and the falling edge of the reference clock signal.

Memory interface circuit, memory storage device and signal generation method

A connection interface circuit, a memory storage device and a signal generation method are disclosed. The connection interface circuit is configured to connect a memory controller to a volatile memory module. The connection interface circuit includes a phase locking circuit, a wire module and a signal interface. The signal interface is coupled between the wire module and the memory controller. The phase locking circuit is configured to receive a first clock signal from the memory controller. The phase locking circuit is further configured to generate a second clock signal according to the first clock signal and a delay feature of the wire module. The wire module is configured to provide a third clock signal to the signal interface according to the second clock signal.

Connection interface circuit, memory storage device and signal generation method

A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

Memory control circuit unit, memory storage device and signal receiving method

A memory control circuit unit, a memory storage device and a reference voltage generation method are provided. The method comprises: detecting a first impedance characteristic of a memory controller via a first connection interface of a memory interface and detecting a second impedance characteristic of a volatile memory via a second connection interface of the memory interface; generating an internal reference voltage according to a detection result; and resolving data signal received by the memory interface according to the internal reference voltage. Therefore, an influence on the internal reference voltage owing to the manufacture deviation of impedance element of the memory controller and/or the volatile memory can be reduced.

Memory control circuit unit, memory storage device and reference voltage generation method

A memory interface, a memory control circuit unit, a memory storage device and a clock generation method are provided. The method includes: receiving a first data strobe signal and a second data strobe signal from a volatile memory, where the first data strobe signal and the second data strobe signal are differential signals corresponding to each other; if a relative relation between a first voltage value of the first data strobe signal and a reference voltage value of a reference voltage signal conforms to a default condition, generating a clock signal in response to the first data strobe signal and the second data strobe signal; and sampling a data signal from the volatile memory based on a raising edge and a falling edge of the clock signal. Thereby, an accuracy for sampling the data signal from the volatile memory can be improved.

Memory interface, memory control circuit unit, memory storage device and clock generation method

An exemplary embodiment of the present disclosure illustrates a method for auto-refreshing memory cells in a semiconductor memory device with an open bit line architecture, wherein the semiconductor memory device comprises M memory banks, and each of the M memory banks has two particular sectors with a same index and L remained sectors with different indices. Two word lines of the two particular sectors with the same index in the memory bank and (M&#x2212;1) word lines of the L remained sectors respectively in the other (M&#x2212;1) memory banks are selected in one cycle. Then, memory cells of the selected word lines are refreshed.

Method for auto-refreshing memory cells in semiconductor memory device and semiconductor memory device using the method

A data input device for use in a memory device to avoid false data being written due to a postamble ringing phenomenon in a write operation is provided. The data input device comprises a buffer, a combinational logic circuit and a flip-flop unit. The buffer receives the data and outputs internal data to the flip-flop unit. The combinational logic circuit receives an external data strobe signal to generate a first data strobe signal and a second data strobe signal. The flip-flop unit stores the data in synchronization with the first data strobe signal and outputs the stored data in synchronization with the second data strobe signal. A last rising edge of the second data strobe signal is generated prior to onset of the postamble ringing on the external data strobe signal, so that a data transferred path in the flip-flop unit is closed prior to onset of the postamble ringing.

Data input device for semiconductor memory device

An anti-fuse circuit including a programmable module, a read module, and a control module is provided. The programmable module has a plurality of data cells. The read module is coupled to the programmable module. During a normal operation, the read module distinguishes which one or more of the data cells are stressed. The control module is coupled to the programmable module. During a stress operation, the control module controls each stressed data cell to be coupled to a high voltage, a low voltage, and a control voltage. The first end of each stressed data cells is coupled to the low voltage, the second end of each stressed data cells is coupled to the high voltage, and the control end of each stressed data cells is coupled to the control voltage during the stress operation.

Anti-fuse circuit

A circuit for generating multiphase clock signals and corresponding indication signals is provided. The circuit includes a multiphase clock generation circuit, a DLL circuit, a timing circuit, and a phase comparison circuit. The multiphase clock generation circuit receives an external clock to provide a plurality of first clock signals, phases of which differ from one another. The DLL circuit receives the external clock signal to provide a second clock signal. The timing circuit receives the second clock signal and a comparison signal to provide a plurality of indication signals. Each of the plurality of indication signals has rising edges which lead the rising edges of a corresponding one of the first clock signals. The phase comparison provides the comparison signal if a delayed phase of the corresponding one of the indication signals is within a phase of one of the first clock signals.

Circuit and method for generating multiphase clock signals and corresponding indication signals

A semiconductor memory device with a self-refresh timing circuit is provided. The semiconductor memory device comprises a plurality of memory banks, a command decoder, a bank address generator, a self-refresh counter, and the self-refresh timing circuit. The self-refresh timing circuit comprises a temperature sensor, a reference voltage source, a comparison circuit, an enable circuit, and an oscillation circuit. The comparison circuit compares a voltage from the temperature sensor with a constant voltage from the reference voltage source and generates a comparison signal. The enable circuit activates the comparison circuit when self-refresh operations for at least one refresh row are completed in all memory cell banks. The oscillation circuit generates a self-refresh clock signal which controls the operating frequency of the bank address generator and the self-refresh counter.

Temperature-dependent self-refresh timing circuit for semiconductor memory device

A method for controlling operations of a delay locked loop (DLL) of a dynamic random access memory (DRAM) is provided herein. A phase detector of the DLL compares an external clock signal with a feedback clock signal to generate a first control signal. A delay line circuit of the DLL delays the external clock signal according to the first control signal. A detector of the DRAM detects variations of the first control signal to determine a length of an enable period of an enable signal. The delay line circuit and the output buffer are active only during the enable period when the DRAM is in a standby mode.

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Hsinchu, Taiwan

Ming-Chien Huang