Moai Electronics Corporation

United Microelectronics Corp.

Faraday Technology Corporation

Ming-Chi Lin

Peng-Fei Lin

Ming-Hung Wang

Chung-Po Hsu

Po-Hao Yu

A receiver and a common-mode voltage calibration method thereof are provided. The receiver includes sensing circuits, a phase comparator, and a self-calibration circuit. The phase comparator compares phase relationships of the latch results at the output terminals of the sensing circuits during a testing period to produce a phase comparison result. During the testing period, the self-calibration circuit provides the same differential signal to the input terminals of these sensing circuits, and sets common-mode levels at the input terminals of these sensing circuits to be different from one another. The self-calibration circuit determines a calibrated common-mode level based on the phase comparison result. The self-calibration circuit sets the common-mode levels at the input terminals of these sensing circuits to be equal to the calibrated common-mode level during a normal operation period.

Receiver and common-mode voltage calibration method thereof

A phase-locked loop (PLL) with novel phase detection mechanism is provided, including a phase frequency detector (PFD), a controller, a digital-to-analog (D2A) module, and a voltage-controlled oscillator/current-controlled oscillator (VCO/ICO), wherein PFD has a reference signal input and an input from the output signal of the VCO/ICO and is connected to the controller, the controller is then further connected to the D2A module, the D2A module converts the control signal from the controller into an analog voltage to control the frequency and phase of VCO/ICO. It is worth noting that the PFD of the present invention has a novel phase detection mechanism so that the phase detection can be accomplished by observing signal level transitions of the reference signal input and a delayed reference signal with respect to the output signal of the VCO/ICO without edge alignment. In addition, the novel phase detection mechanism also allows flexible reference signal input.

Phase-locked loop with novel phase detection mechanism

An apparatus for generating multi-phase clock signals with a ring oscillator is provided, including a first stage phase-blender module and a second stage phase-blender module. The first stage phase-blender module further includes a plurality of differential OP phase-blender circuits. Each differential blender circuit has two signal inputs, and an output signal whose phase is an interpolation of the two input signals. The second stage phase blender module includes a plurality of inverter phase-blender circuits. Each inverter phase-blender circuit receives two output signals from the first stage phase-blender module as inputs, and outputs a clock signal with the interpolated phase of the two output signals of the first stage phase-blender module.

Ring oscillator with a two-stage phase blender for generating multi-phase clock signals

A method for fabricating a semiconductor device to increase the effective concentration of a doped region. A first dopant is implanted into a substrate. A second dopant is implanted into the substrate. The first dopant has a lower diffusion coefficient, a higher energy gap, and a higher atomic mass than those of the second dopant.

Growing community of inventors

Hsinchu, Taiwan

Ming-Chi Lin