Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Cheng Lin

Chun Lin Tsai

King-Yuen Wong

Jiun-Lei Jerry Yu

Yu-Syuan Lin

Chen-Bau Wu

Haw-Yun Wu

Chan-Hong Chern

Chih-Wen Hsiung

Chu Fu Chen

Yun-Hsiang Wang

Liang-Yu Su

Ming-Wei Tsai

Mark Chen

Chao-Hsiung Wang

Hsin-Chieh Huang

Tysh-Bin Liu

Tysh-Bin Lin

Fu-Chih Yang

Ru-Yi Su

Po-Chih Chen

Ming-Fang Lai

Che-Hung Liu

In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer over a base substrate and an active layer over the channel layer. A source and a drain are over the active layer. A gate is over the active layer and laterally between the source and the drain. A dielectric is over the active layer and laterally surrounds the source, the drain, and the gate. A cap structure laterally contacts the source and is disposed laterally between the gate and the source. The source vertically extends to a top of the cap structure.

Cap structure coupled to source to reduce saturation current in HEMT device

In some embodiments, the present disclosure relates to a method of forming a high electron mobility transistor (HEMT) device. The method includes forming a passivation layer over a substrate. A source contact and a drain contact are formed within the passivation layer. A part of the passivation layer is removed to form a cavity. The cavity has a lower portion formed by a first sidewall and a second sidewall of the passivation layer and an upper portion formed by the first sidewall of the passivation layer and a sidewall of the source contact. A gate structure is formed within the passivation layer between the drain contact and the cavity. A cap structure is formed within the cavity.

A semiconductor device includes a transistor, a semiconductor layer, an active region and a conductive layer. The active region is in the semiconductor layer. The conductive layer is configured to maintain a channel in the active region when the transistor is triggered to be conducted.

Semiconductor device having a plurality of III-V semiconductor layers

In some embodiments, the present disclosure relates to a semiconductor device. The semiconductor device includes a channel layer disposed over a base substrate, and an active layer disposed on the channel layer. A source contact and a drain contact are over the active layer and are laterally spaced apart from one another along a first direction. A gate electrode is arranged on the active layer between the source contact and the drain contact. A passivation layer is arranged on the active layer and laterally surrounds the source contact, the drain contact, and the gate electrode. A conductive structure is electrically coupled to the source contact and is disposed laterally between the gate electrode and the source contact. The conductive structure extends along an upper surface and a sidewall of the passivation layer.

Semiconductor device

In some embodiments, the present disclosure relates to a high voltage device that includes a substrate comprising a first semiconductor material. A channel layer that comprises a second semiconductor material is arranged over the substrate. An active layer that comprises a third semiconductor material is arranged over the channel layer. Over the active layer is a source contact spaced apart from a drain contact. A gate structure is arranged laterally between the source and drain contacts and over the active layer to define a high electron mobility transistor (HEMT) device. Between the gate structure and the source contact is a cap structure, which is coupled to the source contact and laterally spaced from the gate structure. The cap structure and a gate electrode of the gate structure comprise a same material.

The present disclosure relates to a semiconductor device including a first high electron mobility transistor (HEMT) device disposed within a semiconductor structure and having a first source, a first drain, and a first gate; a second HEMT device disposed within the semiconductor structure and having a second source, a second drain, and a second gate, the second source coupled to the first drain; and a diode-connected transistor device disposed within the semiconductor structure and comprising a third source, a third gate, and a third drain, the third drain coupled to the second gate.

High voltage cascode HEMT device

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformably over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

High-electron-mobility transistor and manufacturing method thereof

Devices are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.

Low static current semiconductor device

A circuit including a discharging device, a resistive element and a bypass device is disclosed. The discharging device is disposed between a first voltage bus and a second voltage bus. The resistive element is configured to activate the discharging device in response to a high-to-low electrostatic discharge (ESD) event during which the first voltage bus is high in potential relative to the second voltage bus. The bypass device is configured to bypass the resistive element and activate the discharging device in response to a low-to-high ESD event during which the second voltage bus is high in potential relative to the first voltage bus.

Circuit, system and method for electrostatic discharge (ESD) protection

Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a semiconductive substrate. A donor-supply layer is over the semiconductive substrate. The donor-supply layer includes a top surface. A gate structure, a drain, and a source are over the donor-supply layer. A passivation layer covers conformally over the gate structure and the donor-supply layer. A gate electrode is over the gate structure. A field plate is disposed on the passivation layer between the gate electrode and the drain. The field plate includes a bottom edge. The gate electrode having a first edge in proximity to the field plate, the field plate comprising a second edge facing the first edge, a horizontal distance between the first edge and the second edge is in a range of from about 0.05 to about 0.5 micrometers.

Manufacturing method for high-electron-mobility transistor

Devices, systems, and methods are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.

Growing community of inventors

Yilan County, Taiwan

Ming-Cheng Lin