Nan Ya Technology Corporation

Institute of Nuclear Energy Research, Atomic Energy Council, Executive Yuan, R.o.c

Apex Medical Corporation

Nanya Technologies Corporation

Ming-Cheng Chang

Yi-Nan Chen

Jeng-Ping Lin

Wei-Ming Liao

Hui-Min Mao

Yinan Chen

Tse-Yao Huang

Shian-Jyh Lin

Tieh-Chiang Wu

Yi-Chen Chen

Mao-Ying Wang

Neng-Tai Shih

Chih-Yuan Hsiao

Wei-Hui Hsu

Chih-Hsiung Hung

Chung-Lin Huang

Pei-Ing Paul Lee

Ching-Nan Hsiao

Chung-Peng Hao

Chih-Tsan Chien

Hsu-Cheng Fan

Tsai-Yueh Luo

Hung-Chang Liao

Tie-Jiang Wu

Kuan-Yin Chen

Yu-Chang Lin

Jer-Chyi Wang

Chia-Hsiang Hsiao

Ying-Chieh Hsu

Cheng-Liang Peng

Shu-Chi Lin

Tse-Main Kuo

Wen-Bin Shen

Neng Tai Shih

Yi-Chen Lu

Change-Rong Wu

Sheng-Tsong Chen

Hsu Yu-Sheng

Yi-Feng Chang

Hsi-Hua Chang

Hsin-Wei Chen

Chih-Hsiang Wu

The present invention provides an ophthalmic gel and a preparation method thereof. The ophthalmic gel comprises: an antibiotic; a nanocarrier, wherein the nanocarrier is used to load the antibiotic; and a biodegradable matrix, wherein the biodegradable matrix is compatible with the nanocarrier to carry the nanocarrier. When the ophthalmic gel of the present invention is applied to the surface of the cornea and conjunctiva of the eyes, the biodegradable matrix is automatically degraded and the nanocarrier carried by the biodegradable matrix will slowly release the antibiotic, loaded in the nanocarrier, at an appropriate rate to overcome the high-frequency use of general ophthalmic drugs and easily caused blurred vision; the present invention further comprises an ophthalmic gel preparation method.

Ophthalmic gel and preparation method thereof

A humidifier for a respiratory apparatus includes a first cover, a second cover engaged with the first cover and a partition plate. The first cover defines an air inlet. The second cover defines a chamber configured to contain at least some amount of water. A heater is configured to heat the water to generate humidified air in the chamber. The partition plate is partly sandwiched between the first cover and the second cover. The partition plate defines an air outlet. Air input via the air inlet is humidified by being mixed with the humidified air and thereafter ejected through the air outlet. The air entering via the air inlet is divided by the partition plate into a plurality of flows having different flow velocities, thereby form a plurality of flow paths.

Humidifier for respiratory apparatus

A nonvolatile memory device and method for fabricating the same are provided. The method for fabricating the nonvolatile memory device comprises providing a substrate. A tunnel insulating layer and a first conductive layer are formed in the substrate. A trench is formed through the first conductive layer and the tunnel insulating layer, wherein a portion of the substrate is exposed from the trench. A first insulating layer is formed in the trench. A second insulating layer is formed on sidewalls of the first insulating layer. A third insulating layer is conformably formed in the trench, covering the first insulating layer on a bottom portion of the trench and the second insulating layer on the sidewalls of the trench, wherein thickness of the third insulating layer on the sidewalls is thinner than that on the bottom of the trench. A control gate is formed on the third insulating layer in the trench.

Nonvolatile memory device and method for fabricating the same

A method of fabricating a recessed channel access transistor device is provided. First, a semiconductor substrate having thereon a recess etched into a major surface is provided. A gate dielectric layer is then formed on interior surface of the recess. A recessed gate electrode is then formed in and on the recess. The recessed gate electrode comprises a recessed gate portion that is inlaid into the recess and under the major surface, and an upper gate portion above the major surface. An exposed sidewall of the recessed gate electrode is isotropically etched to thereby form a trimmed neck portion having a width that is smaller than that of the recessed gate portion. An exposed sidewall of the trimmed neck portion is then oxidized.

Method of fabricating a recessed channel access transistor device

A method for forming a semiconductor device with a single-sided buried strap is provided. The method includes the steps of providing a substrate with a trench, forming a semiconductor component in a lower portion of the trench to expose a higher portion of the trench, forming a first dielectric layer on a sidewall of the higher portion of the trench, forming a first conductive layer in the trench and adjacent to the first dielectric layer, forming a second dielectric layer on the first dielectric layer and the first conductive layer, forming a plurality of gate structures on the substrate, wherein one of the gate structures on the second dielectric layer is offset for a distance from the second dielectric layer, removing a portion of the second dielectric layer and a portion of the first dielectric layer to form an opening by using the gate structure as a mask, and forming a second conductive layer in the opening to electrically couple to the first conductive layer, whereby the semiconductor device with the single sided buried strap is formed.

Method for forming a semiconductor device with a single-sided buried strap

A trench-type semiconductor device structure is disclosed. The structure includes a semiconductor substrate, a gate dielectric layer and a substrate channel structure. The semiconductor substrate includes a trench having an upper portion and a lower portion. The upper portion includes a conductive layer formed therein. The lower portion includes a trench capacitor formed therein. The gate dielectric layer is located between the semiconductor substrate and the conductive layer. The substrate channel structure with openings, adjacent to the trench, is electrically connected to the semiconductor substrate via the openings.

Trench-type semiconductor device structure

A flash memory includes a substrate with a protrusion, a control gate, two floating gates, and a dielectric layer. The protrusion extends from a top face of the substrate. The control gate is formed on the protrusion of the substrate and extendedly covers opposite sidewalls of the protrusion. The floating gates are respectively formed on top of the protrusion and being on two opposite sides of the control gate. The dielectric layer is sandwiched the control gate and each of the two floating gates. Because of the arcuate control gate used in the flash memory, the controllability of the control gate is increased and the memory cell window is enhanced.

Two-bit flash memory

A memory structure disclosed in the present invention features a control gate and floating gates being positioned in recessed trenches. A method of fabricating the memory structure includes the steps of first providing a substrate having a first recessed trench. Then, a first gate dielectric layer is formed on the first recessed trench. A first conductive layer is formed on the first gate dielectric layer. After that, the first conductive layer is etched to form a spacer which functions as a floating gate on a sidewall of the first recessed trench. A second recessed trench is formed in a bottom of the first recessed trench. An inter-gate dielectric layer is formed on a surface of the spacer, a sidewall and a bottom of the second recessed trench. A second conductive layer formed to fill up the first and the second recessed trench.

Memory structure and method of making the same

A method for forming a semiconductor device includes providing a substrate and forming conductor patterns and openings on the substrate. Next the openings are filled with a mask layer and upper portions of the conductor patterns are etched to form cavities. Following, a portion of the mask layer is removed to form a trench between two neighboring conductor patterns, wherein the trench exposes the substrate and the sidewalls of the two neighboring conductor patterns. Next, an insulating layer on the cavities and the trench is conformably formed, a second conductive layer is formed on the insulating layer and the trench is filled with the second conductive layer.

Method for manufacturing a flash memory device with cavities in upper portions of conductors

A DRAM structure on a silicon substrate has an active area, gate conductors, deep trench capacitors, and vertical transistors. The deep trench capacitors are formed at intersections of the active area and the gate conductors, and each deep trench capacitor is coupled electrically to the corresponding vertical transistor to form a memory cell. The transistor includes a gate, a source in a lateral side of the gate, and a drain in another lateral side of the gate The depth of the drain is different from the depth of the source.

Dynamic random access memory

A memory device with vertical transistors and deep trench capacitors. The device includes a substrate containing at least one deep trench and a capacitor deposited in the lower portion of the deep trench. A conducting structure, having a first conductive layer and a second conductive layer, is deposited on the trench capacitor. A ring shaped insulator is deposited on the sidewall and between the substrate and the first conductive layer. The first conductive layer is surrounded by the ring shaped insulator, and the second conductive layer is deposited on the first conductive layer and the ring shaped insulator. A diffusion barrier between the second conductive layer and the substrate of the deep trench is deposited on one side of the sidewall of the deep trench. A TTO is deposited on the conducting structure. A control gate is deposited on the TTO.

Memory device with vertical transistors and deep trench capacitors and method of fabricating the same

Method for preventing sneakage in shallow trench isolation and STI structure thereof. A semiconductor substrate having a pad layer and a trench formed thereon is provided, followed by the formation of a doped first lining layer on the sidewall of the trench. A second lining layer is then formed on the doped first lining layer. Etching is then performed to remove parts of the first lining layer and the second lining layer so that the height of the first lining layer is lower than the second lining layer. A sacrificial layer is then formed on the pad layer and filling the trench. Diffusion is then carried out so that the doped ions in the first lining layer out-diffuse to the substrate and form diffuse regions outside the two bottom corners of the trench.

Method for preventing leakage in shallow trench isolation

The present invention provides a method for eliminating inverse narrow width effects in the fabrication of DRAM devices. A semiconductor substrate is provided having thereon a shallow trench. The shallow trench surrounds an active area. A non-doped silicate glass (NSG) layer is deposited to fill the shallow trench, and is then etched back to a depth of the shallow trench, thereby exposing a portion of the semiconductor substrate at an upper portion of the shallow trench. A doped dielectric layer is deposited over the remaining NSG layer to cover the exposed semiconductor substrate. A thermal process is then carried out to diffuse dopants of the doped dielectric layer into the semiconductor substrate, thereby forming a doped region at the periphery of the active area in a channel width direction.

Method for eliminating inverse narrow width effects in the fabrication of DRAM device

A deep trench self-alignment process for an active area of a partial vertical cell. A semiconductor substrate with two deep trenches is provided. A deep trench capacitor is formed in each deep trench, and an isolating layer is formed thereon. Each trench is filled with a mask layer. A photoresist layer is formed on the semiconductor substrate between the deep trenches, and the photoresist layer partially covers the mask layer. The semiconductor substrate is etched lower than the isolating layer using the photoresist layer and the mask layer as masks. The photoresist layer and the mask layer are removed, such that the pillar semiconductor substrate between the deep trenches functions as an active area.

Deep trench self-alignment process for an active area of a partial vertical cell

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Taoyuan, Taiwan

Ming-Cheng Chang