Alpha Omega Semiconductor Inc.

Alpha and Omega Semiconductor (cayman) Ltd.

Ming-Chen Lu

Jun Lu

Hamza Yilmaz

Yan Xun Xue

Yan Huo

Yueh-Se Ho

Hua Pan

Zhiqiang Niu

Hongtao Gao

Xiaotian Zhang

Ping Huang

Yuping Gong

Peter L Wilson

Zhi Qiang Niu

Kai Chen

Xiaoguang Zeng

Cheow Khoon Oh

Aihua Lu

Xiaoming Sui

Jianxin Ye

Vincent Xue

Liang Zhao

Demei Gong

Guo Feng Lian

GuoFeng Lian

Alex Niu

Ping Hoang

Jacky Gong

Xiaolian Zhang

A wafer level chip scale package (WLCSP) structure and a manufacturing method are disclosed. The WLCSP structure comprises a semiconductor die and a stack. The stack comprises a protective tape and a molding compound. A portion of a first interface surface between the molding compound and the protective tape is curved. The manufacturing method comprises the steps of forming a semiconductor structure; attaching the semiconductor structure on a dummy wafer; performing a first dicing process using a first cutting tool; depositing a molding compound; removing the dummy wafer; performing a second dicing process with a second cutting tool. A first aperture of the first cutting tool is larger than a second aperture of the second cutting tool. The portion of the first interface surface being curved reduces the possibility of generation of cracks in the WLCSP structure.

Wafer level chip scale package structure and manufacturing method thereof

A power semiconductor package has a small footprint. A preparation method is used to fabricate the power semiconductor package. A first semiconductor chip and a second semiconductor chip are attached to a front side and a back side of a die paddle respectively. Conductive pads are then attached to electrodes at top surfaces of the first and second semiconductor chips. It is followed by a formation of a plastic package body covering the die paddle, the first and second semiconductor chips, and the conductive pads. Side surfaces of the conductive pads are exposed from a side surface of the plastic package body.

Power semiconductor device with small contact footprint and the preparation method

A hybrid packaging multi-chip semiconductor device comprises a lead frame unit, a first semiconductor chip, a second semiconductor chip, a first interconnecting structure and a second interconnecting structure, wherein the first semiconductor chip is attached on a first die paddle and the second semiconductor chip is flipped and attached on a third pin and a second die paddle, the first interconnecting structure electrically connecting a first electrode at a front surface of the first semiconductor chip and a third electrode at a back surface of the second semiconductor chip and a second electrode at the front surface of the first semiconductor chip is electrically connected by second interconnecting structure.

Hybrid packaged lead frame based multi-chip semiconductor device with multiple interconnecting structures

A preparation method of a thin power device comprising the steps of steps S1, S2 and S3. In step S1, a substrate is provided. The substrate comprises a first set of first contact pads and a second set of second contact pads arranged at a front surface and a back surface of the substrate respectively. Each first contact pad of the first set of contact pads is electrically connected with a respective second contact pad of the second set of contact pads via a respective interconnecting structure formed inside the substrate. A through opening is formed in the substrate aligning with a third contact pad attached to the back surface of the substrate. The third contact pad is not electrically connected with the first set of contact pads. In step S2, a semiconductor chip is embedded into the through opening. A back metal layer at a back surface of the semiconductor chip is attached to the third contact pad. In step S3, a respective electrode of a plurality of electrodes at a front surface of the semiconductor chip is electrically connected with said each first contact pad of the first set of contact pads via a respective conductive structure of a plurality of conductive structures.

Preparation method of a thin power device

A method of manufacturing an embedded package comprises attaching a plurality of chips on a pre-mold lead frame; forming a first lamination layer on the plurality of chips, the pre-mold lead frame and a plurality of pins; forming a first plurality of vias and a second plurality of vias through the first lamination layer; forming a respective conductive plug of a plurality of conductive plugs by depositing a respective conductive material in each of the first plurality of vias and each of the second plurality of vias; and electrically connecting the plurality of conductive plugs on the electrodes of the plurality of chips to the plurality of conductive plugs on the plurality of pins.

Embedded package and method thereof

A method of manufacturing a semiconductor package having a small gate clip is disclosed. A first and second semiconductor chips, each of which includes a source electrode and a gate electrode at a top surface, are attached on two adjacent lead frame units of a lead frame such that the lead frame unit with the first chip formed thereon is rotated 180 degrees in relation to the other lead frame unit with the second semiconductor chip formed thereon. A first and second clip sets are mounted on the first and second semiconductor chips, wherein the first clip set is connected to the gate electrode of the first chip, the source electrode of the second chip, and their corresponding leads and the second clip set is connected to the gate electrode of the second chip, the source electrode of the first chip and their corresponding leads.

Semiconductor package with small gate clip and assembly method

A semiconductor device with thick bottom metal comprises a semiconductor chip covered with a top plastic package layer at its front surface and a back metal layer at its back surface, the top plastic package layer surrounds sidewalls of the metal bumps with a top surface of the metal bumps exposing from the top plastic package layer, a die paddle for the semiconductor chip to mount thereon and a plastic package body.

Semiconductor device with thick bottom metal and preparation method thereof

A semiconductor device package comprises a lead frame having a die paddle comprising a first chip installation area and a second chip installation area, a recess area formed in the first chip installation area, and multiple metal pillars formed in the recess area, a notch divides the first chip installation area into a transverse base extending transversely and a longitudinal base extending longitudinally, and separates the recess area into a transverse recess part formed in the transverse base and a longitudinal recess part formed in longitudinal base; a portion of a transverse extending part connecting to an external pin extends into a portion inside of the notch.

Flip chip semiconductor device

Method of hybrid packaging a lead frame based multi-chip semiconductor device with multiple interconnecting structures

An ultrathin power semiconductor package with high thermal dissipation performance and its preparation method are disclosed. The package includes a lead frame unit with a staggered structure including an upper section and a lower section. A thin layer is attached on the surface of the lead frame unit having a plurality of contact holes on the upper section and at least one opening on the lower section. A semiconductor chip is attached on the opening on the lower section of the lead frame unit and then a plurality of metal bumps are deposited, where one metal bump is formed on each contact hole on the upper section and on each of the electrodes on the top surface of the semiconductor chip.

Power semiconductor device and the preparation method

The present invention discloses a new embedded package comprising: a pre-mold lead frame with a plurality of chips attached thereon, where the molding material fills the voids of the lead frame, so that the lead frame is entirely solid; a plurality of pins arranged around the lead frame; a metal clip attached on and electrically connecting the chips together; first laminate layer which covers the chips, the lead frame, a metal clip and pins; conductive plug and extension formed to connect an electrode of a chip to a corresponding pin or to connect the chips together. The new embedded package of the invention with a three-dimensional stack capacity improves the thickness, thermal and electrical properties and the flexible power and logic hybrid design.

A semiconductor package includes a lead frame having a die paddle and a plurality of leads connected to die paddle, where each lead has a lead surface parallel to die paddle and is a continuous extension bending upward from die paddle. A semiconductor chip is mounted on die paddle, where drain metal layer covering a first surface of chip is connected to die paddle, and source metal layer and gate metal layer are located on a second surface opposite to first surface with gate metal layer located at one corner of the second surface. A source metal plate and a gate metal plate are attached on source metal layer and gate metal layer respectively. A molding layer covers lead frame, semiconductor chip, source metal plate and gate metal plate, where lead surface, top surfaces of source metal plate and gate metal plate are exposed from top surface of molding layer.

Growing community of inventors

Shanghai, China

Ming-Chen Lu