Industrial Technology Research Institute

Taiwan Semiconductor Manufacturing Comp. Ltd.

Ming-Che Yang

Yeur-Luen Tu

Cheng-Ta Wu

Yu-Hung Cheng

Pao-Chuan Lin

Po-Yen Chen

Wei-Kung Tsai

Yong-En Syu

Mu-Ping Chen

Chris Chen

Tai-I Yang

Po-Tao Chu

Kun-Ming Huang

Hong-Seng Shue

Ching-Tsai Pan

Po-Shen Chen

Kuo-Hwa Tzeng

Hung-Chun Li

Li-Ling Lee

Chih-Hsin Chen

Wan-Pei Chen

Yeu-Torng Yau

Ching-Tsa Pan

Yeh-Hsiang Ho

Chih-Hsing Fang

Ching-Piao Chen

Kuo-Ing Hwu

Tzu-Cheng Chen

Ke-Dian Wu

Yi-Ying Lee

Tai-Ming Huang

The present disclosure, in some embodiments, relates to a silicon on insulator (SOI) substrate. The SOI substrate includes a dielectric layer disposed over a first substrate. The dielectric layer has an outside edge aligned with an outside edge of the first substrate. An active layer covers a first annular portion of an upper surface of the dielectric layer. The upper surface of the dielectric layer has a second annular portion that surrounds the first annular portion and extends to the outside edge of the dielectric layer. The second annular portion is uncovered by the active layer.

SOI substrate

Structures and formation methods of a semiconductor device structure are provided. The semiconductor device structure includes a supporting substrate. The semiconductor device structure also includes a first carrier-trapping layer covering the supporting substrate. The first carrier-trapping layer is doped with a group-IV dopant. The semiconductor device structure further includes an insulating layer covering the first carrier-trapping layer. In addition, the semiconductor device structure includes a semiconductor substrate over the insulating layer. The semiconductor device structure also includes a transistor. The transistor includes a gate stack over the semiconductor substrate and source and drain structures in the semiconductor substrate.

Semiconductor device structure having carrier-trapping layers with different grain sizes

The present disclosure, in some embodiments, relates to a method of forming an SOI substrate. The method may be performed by epitaxially forming a silicon-germanium (SiGe) layer over a sacrificial substrate and epitaxially forming a first active layer on the SiGe layer. The first active layer has a composition different than the SiGe layer. The sacrificial substrate and is flipped and the first active layer is bonded to an upper surface of a dielectric layer formed over a first substrate. The sacrificial substrate and the SiGe layer are removed and the first active layer is etched to define outermost sidewalls and to expose an outside edge of an upper surface of the dielectric layer. A contiguous active layer is formed by epitaxially forming a second active layer on the first active layer. The first active layer and the second active layer have a substantially same composition.

Process to form SOI substrate

A DC to AC conversion circuit including an inverter, a first inductor, a first capacitor, a second inductor and a second capacitor is provided. The inverter has two input contact points and two output contact points. The input contact points receive a DC signal, and the output contact points output an AC signal. The first terminal of the first inductor is coupled to one of the two output contact points. The first capacitor is coupled to the first inductor in parallel. The first terminal of the second capacitor is coupled to the second terminal of the first inductor, and the second terminal of the second capacitor is coupled to another one of two output contact points. The first terminal of the second inductor is coupled to the first terminal of the second capacitor, and the second terminal of the second inductor is coupled to a load.

DC to AC conversion circuit with resonant circuit

A method for forming a semiconductor device includes forming a hard mask layer over a substrate comprising a semiconductor material of a first conductivity type, and forming a plurality of trenches in the hard mask layer and extending into the substrate. Each trench has at least one side wall and a bottom wall. The method further includes forming at least one barrier insulator layer along the at least one side wall and over the bottom wall of each trench, removing the at least one barrier insulator layer over the bottom wall of each trench, and filling the plurality of trenches with a semiconductor material of a second conductivity type.

Super junction trench metal oxide semiconductor device and method of making the same

A DC-AC converter is provided. The DC-AC converter includes a time-varying DC power generating circuit, an AC power generating circuit and a transmission capacitor. The time-varying DC power generating circuit is controlled by a pulse width modulation (PWM) signal to transform a DC source into a time-varying DC power. With reference to the time-varying DC power, the AC power generating circuit is controlled by a first polarity switching and a second polarity switching signal to generate an AC power. The transmission capacitor, coupled to the time-varying DC power generating circuit and the AC power generating circuit, transmits the time-varying DC power from the time-varying DC generating circuit to the AC power generating circuit.

DC-AC converter and conversion circuit

An light emitting diode (LED) control, a plurality of duty cycle signals corresponding to a plurality of LEDs are stored in a dual-port memory by memory mapping. By sampling, the stored duty cycle signals are outputted to generate a plurality of parallel single-bit data each having one single bit. After the single-bit data are converted by a data transmission module, each bit of the single-bit data is serially outputted to a drive module to drive the LEDs. Thus, the ON duty cycles of the LEDs are modulated by pulse width modulation (PWM), light emitted from the LEDs are mixed in time-domain, and the brightness of the LEDs can be controlled.

Control circuit and method for backlight sources, and image display apparatus and lighting apparatus using the same

An N-phase full bridge power converter, comprising: a load device; a plurality of bridge legs, each being composed of two power switches; a plurality of transformers, each being coupled between two nodes each disposed between two power switches in two adjacent bridge legs on its primary side and coupled to the load device on its secondary side; and a plurality of inductors, each being connected between a node and the primary side of one of the transformers corresponding thereto.

N-phase full bridge power converter

The configurations of a non-contact power supply and a coupling detection method thereof are provided. The proposed non-contact power supply includes a detachable transformer including a primary side, a current sensor coupled to the primary side and sensing a primary side current and a controller coupled to the current sensor, receiving the current and determining whether the power supply is under a coupling status according to the current.

Non-contact power supply having built-in coupling detection device and coupling detection method thereof

A compensating circuit for compensating the terminal voltage on the armature in a sensorless type DC brushless motor apparatus is described. The driving circuit of the motor apparatus outputs a three-phase power, and each phase is connected with a compensating circuit. The compensating circuit has a reference voltage, a resistance device, a diode device, a differential amplifier and a processor. The two terminals of the resistance device are respectively connected to the reference voltage and the anode of the diode device. The cathode of the diode device is connected to an output of the three-phase power supply. The two input terminals of the differential amplifier are respectively connected to the two terminals of the resistance device. The processor accepts the signal output from the differential amplifier and then calculates and outputs a compensating voltage.

Voltage compensating circuit for a sensorless type DC brushless motor

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Hsinchu, Taiwan

Ming-Che Yang