Industrial Technology Research Institute

Quantum Corporation

Ming-Che Hsieh

Ra-Min Tain

John H Lau

Ming-Ji Dai

Wei Yu Li

Chih-Kuang Yu

Chun-Kai Liu

Chun-Chieh Chen

Po-Ting Chen

Yu-Lin Chao

Heng-Chieh Chien

Shu-Jung Yang

Chih-Yuan Cheng

Suh-Yun Feng

Rong-Chang Fang

Chun-I Wu

Jui-Feng Hung

An image conversion device includes: a lens module configured to allow passing of image light beams of an object, an optical waveguide element configured to transmit the image light beams to a light processing component, and an image sensor configured to convert the image light beams into digital image signals. By changing image capturing and image forming methods, higher image quality may be achieved and expanding flexibility may be maintained.

Image conversion device for digital image signals

A method of manufacturing a device with a optical component disposed thereon, including following steps of: preparing a substrate, the substrate including a signal guide and an electric conductive structure; and mounting an optical component on the substrate and corresponding a light transmission face of the optical component to the signal guide, wherein the optical component and the substrate is connected by an adhesive material and the optical component is electrically connected with the electric conductive structure. A transmission device being made by the method of manufacturing the device with the optical component disposed thereon as described above is further provided.

Method of manufacturing device with optical component disposed thereon and transmission device manufactured by the same

A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.

Fabricating method of semiconductor device

A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.

Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor

By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.

Filled through-silicon via with conductive composite material

Fabricating method and testing method of semiconductor device and mechanical integrity testing apparatus

A stacked-chip packaging structure includes chip sets, a heat sink, a substrate, a circuit board, and solder balls. The chip sets are stacked together, each of which has a heat-dissipation structure and a chip. The heat-dissipation structure has a chip recess, through holes arranged in the chip recess, and an extending portion extending from the chip recess. The chip disposed in the chip recess has bumps. Each bump on the chip is correspondingly disposed in one of the through holes of the heat-dissipation structure. The extending portion of the heat-dissipation structure of each chip set contacts that of the neighboring chip set. The heat sink and the substrate are disposed at two opposite sides of the chip sets, respectively. The circuit board is below the substrate. The solder balls are between the circuit board and the substrate.

Stacked-chip packaging structure and fabrication method thereof

A thermoelectric conversion device includes a hot terminal substrate, a cold terminal substrate and a stacked structure. The stacked structure is disposed between the hot terminal substrate and the cold terminal substrate. The stacked structure includes thermoelectric conversion layers each including a thermoelectric couple layer, a first conductive layer and a second conductive layer, a first heat-conductive and electrically insulating structure and a second heat-conductive and electrically insulating structure. Each of the thermoelectric conversion layers is arranged in the stacked structure. The first conductive layer includes first conductive materials and is arranged on tops of P/N type thermoelectric conversion elements. The second conductive layer includes second conductive materials and is arranged on bottoms of the P/N type thermoelectric conversion elements. The first heat-conductive and electrically insulating structure is connected between two adjacent first conductive layers. The second heat-conductive and electrically insulating structure is connected between two adjacent second conductive layers.

Thermoelectric conversion device

The disclosure provides a chip package structure and method for fabricating the same. The chip package structure includes at least one chip having at least one through via. At least one stress buffering structure is disposed in the through via. The stress buffering structure includes a first gasket and a second gasket. A supporting pillar has two terminals respectively connected to the first gasket and the second gasket. The cross-sectional area of the supporting pillar is smaller than areas of the first gasket and the second gasket. A buffering layer is sandwiched between the first gasket and the second gasket, surrounding a sidewall of the supporting pillar. An insulating layer is disposed on the through via, surrounding a sidewall of the stress buffering structure.

Chip package structure and method for fabricating the same

A chip package structure includes a substrate, a chip, a thermal conductive layer, a plurality of signal contacts, and a molding compound. The substrate includes a plurality of first thermal conductive vias, a connecting circuit, and a plurality of signal vias electrically connected to the connecting circuit, and the substrate has a chip disposing region. The chip is disposed on the chip disposing region of the substrate and electrically connected to the signal vias through the connecting circuit. The thermal conductive layer is disposed over the substrate, connected to the first thermal conductive vias, and located above the chip disposing region. Besides, the thermal conductive layer has first openings exposing the signal vias. The signal contacts are respectively disposed in the first openings and connected to the signal vias. The molding compound encapsulates the chip.

Growing community of inventors

Kaohsiung, Taiwan

Ming-Che Hsieh