Macronix International Co., Ltd.

Ming-Chao Lin

Han-Sung Chen

Chun-Hsiung Hung

Wen-Feng Hsueh

A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a cell and executing a program and program verify operation for the cell, including applying a sequence of program pulses and performing program verify steps. The sequence includes a starting pulse having a starting magnitude. The program verify steps use a program verify level. The method also comprises determining the starting magnitude for a next cell as a function of a magnitude of the program pulse in an instance of the program verify step in which the current cell passes verify at the program verify level.

Programming scheme for next starting pulse based on a current program pulse for improving programming speed

An integrated circuit with memory can operate with reduced latency between consecutive operations such as read operations. At a first time, a first operation command is finished on a memory array on an integrated circuit. At a second time, a second operation command is begun on the memory array. A regulated output voltage from the charge pump is coupled to word lines in the memory array. From the first time to the second time, a regulated output voltage is maintained at about a word line operation voltage such as a read voltage.

Memory operation latency control

A non-volatile memory array storing data and ECCs includes error correcting logic. A data set can be read by performing iterations including sensing data using a read bias, and producing an indication of errors in the sensed data. A first iteration uses a first read bias. In each iteration, if the indication in a current iteration is less than a threshold, then the data is output from the selected cells sensed in the present iteration. If the indication in the current iteration exceeds the threshold, then another iteration is performed using a moved read bias, unless the indication in the current iteration shows an increase in errors relative to a previous iteration, in which case then sensed data from the previous iteration is output. Double buffering logic can be used to store sensed data during a current and a previous iteration.

Memory with error correction configured to prevent overcorrection

A method for programming a memory including a plurality of memory cells is provided. The method comprises selecting a current cell and executing a pre-program verify operation at a first program verify level. The method comprises executing a program and program verify operation for the current cell, including applying a sequence of program pulses and performing program verify steps. The sequence includes a starting pulse having a starting magnitude. The program verify steps use a second program verify level. The method also comprises determining the starting magnitude for a next cell as a function of a magnitude of the program pulse in an instance of the program verify step in which the current cell passes verify at the second program verify level.

Incremental step pulse programming (ISPP) scheme capable of determining a next starting pulse based on a current program-verify pulse for improving programming speed

A program method, applied in a flash memory, includes the following steps. Firstly, a first memory sector and a second memory sector are selected, wherein the first and the second memory sectors respectively correspond to a first word line and a second word line. Next, a first operation phase and a second operation phase are determined. Then, the first word line is biased with a first setup voltage, and the second word line is driven in one of a program operation and a program-verification operation, in the first operation phase. After that, the second word line is biased with a second setup voltage, and the first word line is driven in the other one of the program operation and the program-verification operation in the second operation phase.

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Taichung, Taiwan

Ming-Chao Lin