Realtek Semiconductor Inc.

Ming-An Wu

Chun-Chieh Chan

Chia-Hao Chang

Tai-Jung Wu

Chien-Hsun Lu

Hung-Shao Chen

The present disclosure discloses a video interface conversion device that includes a first and a second interface transmission circuit, a color conversion circuit and an image compression circuit. The first and the second interface transmission circuit are respectively electrically coupled to an image source and a display terminal. The second interface transmission circuit negotiates a maximum output bandwidth with the display terminal such that the first interface transmission circuit compares an input data bandwidth of a data signal received from the image source and the maximum output bandwidth. When the maximum output bandwidth is smaller than the input data bandwidth, an image compression and/or a color coding conversion is performed on the data signal, and the data signal having the processed input data bandwidth being smaller than or equal to the maximum output bandwidth is further transmitted by the second interface transmission circuit to the display terminal.

Video interface conversion device and method

A method for switching audio-visual interfaces and a circuit system are provided. The circuit system is disposed in a sink device. A protocol layer circuit of each of audio-visual interfaces in the sink device includes a status and control data channel control module, which is used to respond to the signals sent by the video sources continuously when the sink device is connected with audio-visual sources via the audio-visual interfaces. The multiple video sources can accordingly send FRL (fixed rate link) signals to the sink device in response to responses made by the sink device. The protocol layer circuit includes an FRL audio-visual packet detection module that starts to detect a rate of an FRL and resolve audio-visual packets for obtaining audio-visual data for the audio-visual interface that the sink device switches to.

Method for switching audiovisual interfaces and circuit system

The present invention discloses a signal enhancement relay apparatus is provided. A display data channel stretching circuit includes a direct and an indirect channels. A snooper circuit is disposed at the direct channel. The indirect channel includes a master and a slave paths having a master and a slave transmission circuits disposed thereon. The direct channel is selected under a default passive mode such that a snooper link bridging handler circuit is enabled to monitor a display data transmission on the direct path through the snooper circuit, to perform a channel link bridging process corresponding to a data enhancement transmission channel accordingly. When the channel link bridging process under the passive mode fails, the indirect channel is selected under an active mode such that a intervening link bridging handler circuit t is enabled to access the display data transmission on the master and the slave paths respectively through the master and the slave transmission circuits, to perform the channel link bridging process respectively.

Signal enhancement relay apparatus and method

A detection circuit and a wake-up method are provided. The detection circuit is adapted to a high definition multimedia interface (HDMI) receiver that enters a power-saving mode in a fixed rate link (FRL) mode to detect whether or not an HDMI transmitter starts to transmit video packets through the FRL. The detection circuit includes a signal detection circuit detecting whether or not signal exists on the FRL and an FRL packet determination circuit determining whether or not the FRL packets are the video packets according to a variable value characteristic of the video packets and/or a fixed value characteristic of gap packets. An existence of the signal on the FRL indicates an existence of FRL packets on the FRL. When the FRL packets are the video packets, the FRL packet determination circuit wakes the HDMI receiver from the power-saving mode to resolve the video packets and display videos.

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Hsinchu, Taiwan

Ming-An Wu