Intel Corporation

Intel China Ltd.

Minerva M Yeung

Yen-Kuang Chen

Eric L Debes

William W Macy, Jr

Matthew J Holliman

Boon-Lock Yeo

Huy Van Nguyen

Julien Sebot

Scott A Craver

Igor V Kozintsev

Rainer Wolfgang Lienhart

Shreekant S Thakkar

Gary R Bradski

Patrice L Roussel

Dan Li

Chao Huang

Eric Li

Robert Du

Ping Du

Xing Tang

Li-Cheng Tai

Nan N Li

Lingfei Song

Xing Room 1201 Bldg 39 Tang

A state of an application running in a system is monitored. The monitoring of the application states includes monitoring one or more buffers associated with the application. Dispatch of one or more threads in the system is controlled. At least one thread in the system is associated with the application. Resources in the system are managed based at least on the state of the application and the state of the one or more threads in the system.

Methods for reducing energy consumption of buffered applications using simultaneous multi-threading processor

Method, apparatus, and program means for performing bitstream buffer manipulation with a SIMD merge instruction. The method of one embodiment comprises determining whether any unprocessed data bits for a partial variable length symbol exist in a first data block is made. A shift merge operation is performed to merge the unprocessed data bits from the first data block with a second data block. A merged data block is formed. A merged variable length symbol comprised of the unprocessed data bits and a plurality of data bits from the second data block is extracted from the merged data block.

Bitstream buffer manipulation with a SIMD merge instruction

A method and apparatus for performing bi-linear interpolation and motion compensation including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two or more lines of 2n+1 content byte elements may be shuffled to generate a first and second packed data respectively including at least a first and a second 4n byte elements including 2n&#x2212;1 duplicated elements. A third packed data including sums of products is generated from the first packed data and packed byte coefficients by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements and packed byte coefficients by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed, and may be rounded and averaged.

Method and apparatus for efficient bi-linear interpolation and motion compensation

A system for associating a selected object on any printed material to a valid response provided by a computer system includes a maker component to define an object on a page of printed material, and to link a position of the object on the page, the contents of the page, and the response to be performed by a computer system. The system also includes a pointing device to determine a position on the printed material, a communicating device to transmit the position to the computer system, and a player component to correlate the position to selected digital content associated with the printed materials, the selected digital content being accessible by the computer system; and to provide a valid response to a user based at least in part on the position and the correlated content, wherein the valid response includes at least one of rendering audio content, rendering video content, rendering image content, and performing an action by the computer system.

Creating responses for an electronic pen-computer multimedia interactive system

The fluency of a spoken utterance or passage is measure and presented to the speaker and to others. In one embodiment, a method is described that includes recording a spoken utterance, evaluating the spoken utterance for accuracy, evaluating the spoken utterance for duration, and assigning a score to the spoken utterance based on the accuracy and the duration.

Measurement of spoken language training, learning and testing

Method, apparatus, and program means for performing a parallel table lookup using SIMD instructions. The method of one embodiment comprises loading a table having a set of L data elements. A determination of whether the table fits into a single register is made. A data lookup into the table is performed with a packed data shuffle operation if the determination indicates that the table does fit into a single register. The table is divided into a plurality of sections if the table does not fit into a single register. Each of the sections is sized to fit into a single register. A plurality of packed data shuffle operations are executed on the plurality of sections to look up data in the table.

Method and apparatus for parallel table lookup using SIMD instructions

A method and apparatus for performing matrix transformations including multiply-add operations and byte shuffle operations on packed data in a processor. In one embodiment, two rows of content byte elements are shuffled to generate a first and second packed data respectively including elements of a first two columns and of a second two columns. A third packed data including sums of products is generated from the first packed data and elements from two rows of a matrix by a multiply-add instruction. A fourth packed data including sums of products is generated from the second packed data and elements from two more rows of the matrix by another multiply-add instruction. Corresponding sums of products of the third and fourth packed data are then summed to generate two rows of a product matrix. Elements of the product matrix may be generated in an order that further facilitates a second matrix multiplication.

Method and apparatus for computing matrix transformations

Growing community of inventors

Sunnyvale, CA, United States of America

Minerva M Yeung