Link Laboratory Inc.

Hitachi, Ltd.

Hitachi Vlsi Engineering Corp.

Hitachi Electronics Services Co. Ltd.

Mineo Ogino

Takahiko Kozaki

Yoshito Sakurai

Noboru Endo

Hiroshi Kuwahara

Eiichi Amada

Kenichi Asano

Toshihito Ochi

Tadayuki Ichiba

Hiromi Kawaguchi

Naoyoshi Machida

Masato Tachibana

Masahiko Kurata

Method for collecting information about physical constitution of lan

A switching system exchanges communication information as fixed length cells between a plurality of incoming and outgoing highways. The fixed length cells each have a plurality of data portions with one data portion designated as a header portion for containing switching information. An address generating circuit generates read addresses and write addresses in response to the header portion of each cell and a control circuit. The plurality of cells from the incoming highways are simultaneously rotated in a rotation matrix with each of the cell's data portions rotated to a unique internal path. The data portions are then transmitted to identical write addresses in a plurality of memories via delay circuitry. The write addresses are transmitted through shift registers to the plurality of memories to allow the data portions of a single cell to occupy identical addresses within a plurality of memories. The control circuitry determines the correct outgoing highway for each cell based upon information contained within the header portion of each cell or a routing table. The data portions are then read out of read addresses in the plurality of memories and rotated by another rotation matrix. The rotated data portions reform the fixed length cell along a determined outgoing highway.

Switching system

A fixed-length packet switching system, in which fixed-length packets (cells) each composed of a header portion and a data portion are received from a plurality of input lines, and after conversion of the header portions, the received packets are transmitted onto selected ones of output lines designated by their header portions. The system includes a buffer memory having a first buffer area composed of a plurality of subsidiary areas for accumulating cells correspondingly to the output lines, and a second buffer area for accumulating broadcast cells to be transmitted to selected ones of the plurality of output lines; a packet reading circuit for reading the cells from the first buffer area successively corresponding to the output lines and for reading the broadcast cell from the second buffer area at a predetermined frequency; and a broadcast control circuit for reproducing a plurality of broadcast cells from the broadcast cells read from the second buffer area and for transmitting the plurality of reproduced broadcast cells, instead of the cells read from the first buffer area, onto the output lines. The buffer memory is divided into a plurality of buffer areas each corresponding to a respective output line and a packet writing circuit generates addresses sequentially for the respective buffer areas to store cells in a buffer area according to the header portion thereof.

Cell switching system of asynchronous transfer mode

Growing community of inventors

Hanno, Japan

Mineo Ogino