Oki Electric Industry Co., Ltd.

Oki Semiconductor Co., Ltd.

Zentel Japan Corporation

Mineo Noguchi

Bunsho Kuramori

Takashi Kubo

Hitoshi Yamada

Masaru Haraguchi

Jun Setogawa

Akihiro Hirota

Hironori Iga

Masahiro Ishihara

Mitsuru Yoneyama

A semiconductor memory device is provided with a row control circuit, in order to dissolve a Row Hammer issue. The row control circuit is configured to: (A) latches one of (a) a target address upon issuing of an ACTIVE command to the semiconductor memory device, and (b) a row address of a victim cell in which data of a memory cell is affected by the target address, as a victim address by using a predetermined row address latch method; and then, (B) refreshes the victim cell having the victim address by a predetermined refresh method upon issuing of a REFRESH command.

Semiconductor memory device for preventing occurrence of row hammer issue

A bandgap reference circuit inputs a reference potential trimming signal therein, generates a reference potential using PN-junction diode characteristics and generates a first temperature-dependent potential dependent on the temperature. A subtraction amplifier circuit inputs the reference potential, the first temperature-dependent potential and a subtracter trimming signal therein and generates a second temperature-dependent potential amplified by subtraction amplification of both a constant bias potential obtained by performing multiplication on the reference potential and the first temperature-dependent potential. An A/D converter inputs the reference potential and the second temperature-dependent potential therein and A/D-converts the second temperature-dependent potential by reference to the reference potential to thereby output temperature decision results.

Temperature sensor

An output signal ZA of NANDis given to a first input of NANDand is given to a second input of the above NAND, simultaneously through a delay circuit. Furthermore, an output signal ZB of the NANDis given to the first input of NANDand is given to the second input of NAND, simultaneously through a delay circuit. The delay circuit includes a charging and discharging circuit consisting of a NMOShaving the conductivity controlled by a voltage VN depending on a temperature signal from a temperature-dependent current sourceand a capacitor, and a NMOSbeing turned on/off by the voltage of the above capacitor. By setting temperature characteristics of the voltage VN and temperature characteristics of the threshold voltage of the NMOSso as to cancel each other, the oscillation frequency variation of the oscillation circuit consisting of astable multi-vibrators can be restrained.

Oscillation circuit with temperature-dependent current source

A step-down power supply receives an external power supply voltage and supplies power at a reduced voltage from an output node to a load. The power supply also receives a reference voltage and a control signal indicating the whether the load is active or not. The reduced power supply voltage is held equal to the reference voltage by adjustment of the voltage at an internal control node. To prevent fluctuations in the reduced power supply voltage at active-inactive transitions of the load, the power supply includes circuitry for pulling the voltage at the internal control node both up and down, circuitry for leaking current from the output node to ground, circuitry for temporarily raising and lowering the reference voltage, or a capacitor coupling the reference voltage signal line to the control signal line.

Step-down power supply

An I/O interface circuit immediately close to a bank having a plurality of memory cells and an I/O circuit is directly connected to data line pairs via a switching circuit. Another I/O interface circuit is connected to other data line pairs via switching circuits and data bus pairs. Consequently the number of lines of the data bus pairs provided within the chip of the semiconductor integrated circuit is half of the number in the prior art, and the chip area can be reduced.

Semiconductor integrated circuit

A semiconductor memory device includes a reference voltage circuit which has an external power supply voltage input thereto and outputs a reference voltage. A standard voltage circuit has the reference voltage input thereto, and outputs a standard voltage. A voltage detecting circuit includes a PMOS transistor having a gate connected to the standard voltage, a source connected to a test mode signal pad, and a drain connected to the ground voltage via a resistor. A test mode control circuit outputs a test mode operation signal, an input terminal of the test mode control circuit being connected to a node of the voltage detecting circuit that is between the PMOS transistor and the resistor.

Semiconductor memory circuit

The aim of the present invention is to provide a power supply control system which enables an improvement in the response speed of the voltage sensor section to be achieved at a low level of power consumption. The present invention comprises: a voltage booster circuit for boosting voltage; a voltage sensor section which operates on the basis of voltage output from the voltage booster circuit; and a threshold value altering circuit which lowers a threshold value of the voltage sensor section when the voltage booster circuit is operating, and raises a threshold value of the voltage sensor section when the operation of the voltage booster circuit is halted.

Growing community of inventors

Tokyo, Japan

Mineo Noguchi