Samsung Electronics Co., Ltd.

Mincheol Kwon

Sangwon Jung

Dong Jun Shin

Sun-Mi Yoo

Disclosed is an operating method of a storage device which includes a plurality of nonvolatile memory chips. The method includes providing, at the storage device, information of a capacity of each of the plurality of nonvolatile memory chips to an external host device, receiving, at the storage device, information of a plurality of groups from the external host device, performing a reset after receiving the information of the plurality of groups, mapping, at the storage device, the plurality of nonvolatile memory chips with the plurality of groups, and configuring the plurality of nonvolatile memory chips so as to correspond to the plurality of groups, after performing the reset.

Storage device, operating method of storage device, and electronic device including storage device

An method of a storage device configured to communicate with an external device through an interface channel includes: storing a throttling predefined table (PDT) including a relationship between target performances and workload characteristics; detecting that a first workload characteristic has changed; determining whether to update the PDT; when it is determined to update the PDT, monitoring a performance of the storage device; updating the PDT to include at least one new value for the workload characteristics and an additional target throttling performance value, based on a calculated monitored performance and the changed value of the first workload characteristic; controlling an operation parameter based on the updated PDT such that the interface channel has a first throttling performance corresponding to the additional target throttling performance value; receiving a first request through the interface channel from the external device; and processing the first I/O request through the interface channel.

Storage device and operation method thereof

A solid state drive (SSD) comprises an input/output interface and a memory controller. The input/output interface stores a plurality of input/output commands. The memory controller comprises first and second input/output contexts and an input/output scheduler. The first and second input/output contexts process input/output commands from the input/output interface in an alternating sequence. The input/output scheduler schedules operations of the first and second input/output contexts. In particular, the input/output scheduler suspends execution of a first input/output command by the first input/output context upon determining that an execution time of the first input/output command exceeds an interval before a deadline time. After suspending execution of the first input/output command, the input/output scheduler transmits a second input/output command to the second input/output context.

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Yongin-si, South Korea

Mincheol Kwon