Kabushiki Kaisha Toshiba

Minakshisundaran Balasubramanian Anand

Hideki Shibata

Masaki Yamada

Tadashi Matsuno

Katsuya Okumura

Hisashi Kaneko

Kazuyuki Higashi

Akihiro Kajita

Naofumi Nakamura

Tetsuo Matsuda

Noriaki Matsunaga

Tadashi Iijima

Masahiro Inohara

Hiroshi Ohtani

In the present invention, the bonding pad is formed in a lattice-like shape. Directly underneath the passivation layer, the etching stopper layer is provided. An opening is made through the passivation layer and the etching stopper layer so as to expose the bonding pad. The cavity sections of the lattice-like shape of the bonding pad are filled with the insulating layer. The bonding wire is connected to the lattice-shaped bonding pad. With this structure, the bonding error of the device manufactured by the damascening process can be avoided.

Semiconductor device having a plurality of conductive layers

Semiconductor device and method of manufacturing the same

A semiconductor device manufacturing method comprises a step of forming a trench to a first insulation film formed on a semiconductor substrate, and forming a lower level wiring in the trench, a step of forming at least one conductive layer on the semiconductor substrate to coat the lower level wiring, a step of forming at least one thin film layer on the conductive layer, a step of forming a hard mask by patterning the thin film, a step of etching the conductive layer by using the hard mask as an etching mask, and forming a conductive pillar-shaped structure, whose upper surface is covered with the hard mask, on the lower level wiring, a step of forming a second insulation film on the semiconductor substrate so that the pillar-shaped structure is buried, a step of forming a wiring trench in which at least the hard mask is exposed, and a step of burying a conductor into the wiring trench after the hard mask is removed, and forming an upper level wiring in the wiring trench.

Semiconductor device manufacturing method and semiconductor device

Wires are provided on an insulating layer, reaching the source region and drain region of a MOS transistor. Each wire is composed of a conductor and a barrier layer covering the surfaces of the conductor. An insulating layer is mounted on the wires, an insulating layer on the insulating layer, and an insulating layer on the insulating layer. Cavities are provided among the wires. The cavities are filled with air or a mixture gas of oxygen and carbon dioxide. Wires are provided on the insulating layer. Cavities are provided among the wires. These cavities are filled with air or a mixture gas of oxygen and carbon dioxide.

Feasible, gas-dielectric interconnect process

Wiring of a non-uniform density is laid out on a chip. Then, the chip is virtually divided into a plurality of sub chips. The wiring density of each sub chip is obtained to obtain the density distribution function of wiring. After that, an index indicative of variations in the density of wiring is obtained on the basis of the density distribution function, thereby determining whether or not the index falls within an allowable range. If the index is out of the allowable range, the density distribution function is repeatedly updated until the index falls within the allowable range. Dummy wiring is provided on a region obtained by subtracting a region corresponding to the initial density distribution function from a region corresponding to the last density distribution function.

Method of designing dummy wiring

The present invention provides a way how to use a technique for forming the contact of a diffusion layer in a self-alignment manner in combination with a salicide technique. The most important finding in the way is that when an insulating film is deposited over the entire surface, the insulating film deposited on a shared diffusion layer which is present in a depressed portion between two electrodes is thinner in a natural course of events than that deposited on open-surfaces of the two electrodes. When such an insulating film different in thickness is etched, the relatively thin insulating film formed on the shared diffusion layer is substantially completely removed, whereas the relatively thick insulating film formed on the two electrodes is not completely removed and remains as a thin film. Hence, if the silicide layer is formed on the diffusion layer and the electrodes before the insulating film is deposited, the insulating film formed on the shared diffusion layer is selectively removed while leaving the insulating film formed on the electrodes.

Method of manufacturing semiconductor device having a self aligned

A semiconductor device includes a semiconductor substrate having a main surface, and a multi-layered wiring layer formed on the main surface of the semiconductor substrate, the multi-layered wiring layer having a plurality of wiring layers insulatively laminated, wherein the melting points of the plurality of wiring layers are set gradually lower in a direction towards the higher-level side.

Semiconductor device and method for manufacturing the same

In a method of manufacturing a semiconductor device, when a copper diffusion preventing film portion on the connecting hole bottom portion is to be removed, a film thickness of other portion of the copper diffusion preventing film not to be removed is more thickly formed than that of the to-be-removed copper diffusion preventing film portion on the connecting hole bottom portion, thereby only the copper diffusion preventing film portion to be removed can be removed. The method can extend a durable length of time of a wire and can reduce a resistance of the metal wires in a connecting hole bottom portion by removing a copper diffusion preventing film on the bottom portion of the connecting hole.

Growing community of inventors

Yokohama, Japan

Minakshisundaran Balasubramanian Anand