Texas Instruments Corporation

Micron Technology Incorporated

Min Yu Chan

Siu Waf Low

Jing Sua Goh

Chee Kiang Yew

Boon Pew Chan

Kian Teng Eng

Pak Hong Yee

Pang Hup Ong

Tuck Fook Toh

Yong Poo Chia

Meow Koon Eng

Chew Weng Leong

Jeffrey Tuck Fook Toh

Suan Jeung Boon

Wei Zhou

Swee Kwang Chua

Anthony Louis Coyle

Bok Leng Ser

Yong Khim Swee

Kim Hoch Tey

Jeffrey Tuck Fock Toh

Chee Klang Yew

Sui Waf Low

A microelectronic component package includes a plurality of electrical leads which are coupled to a microelectronic component and which have exposed lengths extending outwardly beyond a peripheral edge of an encapsulant. A plurality of terminals may be positioned proximate a terminal face of the encapsulant and these terminals may be electrically coupled to the same leads. This can facilitate connection of the microelectronic component to a substrate using the leads as a conventional leaded package. The terminals, however, can facilitate stacking of the leaded package with one or more additional microelectronic components, e.g., a BGA package.

Packaged microelectronic components

Packaged microelectronic devices and methods of packaging microelectronic devices are disclosed herein. In one embodiment, the device includes an image sensor die having a first side with a bond-pad, an active area on the first side, and a second side opposite the first side. The device further includes a window at the first side of the image sensor die and a lead mounted to the second side of the image sensor die. The window is radiation transmissive and positioned over the active area of the image sensor die. The lead is electrically coupled to the bond-pad on the image sensor die.

Packaged image sensing microelectronic devices including a lead and methods of packaging image sensing microelectronic devices including a lead

A high density unit ( ) comprising a first integrated circuit package ( ) comprising a carrier ( ) having first and second sides ( ), a silicon chip ( ) attached by an adhesive layer ( ) and solder bonding ( ) electrically connecting the silicon chip ( ) to the carrier ( ) stackably and electrically connected to a second integrated circuit package ( ), is disclosed.

Method of fabricating thin integrated circuit units

A method and apparatus for producing an integrated circuit package ( ) comprising a substrate ( ) having an opening ( ) and first and second surfaces ( ), a plurality of routing strips ( ) being integral with the substrate ( ) and extending into the opening ( ), a plurality of pads ( ) disposed on the first and second surfaces ( ) are electrically connected with at least one of the routing strips ( ), wire bonding ( ) electrically connecting at least one bonding pad ( ) to at least one of the routing strips ( ) and a silicon chip ( ) attached to the printed circuit board ( ) by an adhesive material ( ) that provide a seal between silicon chip ( ) and printed circuit board ( ) is disclosed.

Method for adhering and sealing a silicon chip in an integrated circuit package

Integrated circuit package

A high density unit (,) comprising a first integrated circuit package (,) comprising a carrier (,) having first and second sides (,), a silicon chip (,) attached by an adhesive layer (,) and solder bonding (,) electrically connecting the silicon chip (,) to the carrier (,) stackably and electrically connected to a second integrated circuit package (,), is disclosed.

Stacked double sided integrated circuit package

A method and apparatus for fabricating small form factor semiconductor chips having high temperature resistance, good humidity and chemical resistance and good dielectric properties. The semiconductor chip includes a lead frame (,) attached to an integrated circuit die (,) by a lead-on-chip (LOC) method. Wire bonds (,) are employed to connect the integrated circuit die (,) to conduction leads (,) on the lead frame (,). After the wire bonding process, the surface of the wire bonded integrated circuit is encapsulated with a layer of resin (,) using either a direct dispensing method or by a screen printing method. The encapsulated integrated circuit may then be cured and functionally tested.

Encapsulate resin LOC package and method of fabrication

A packaged semiconductor device and a method for burn-in and testing are disclosed. The package comprises a carrier having a pattern of contact pads for electrical connection, and also a pattern of testing pads for electrical characterization such that their location, size and composition allows a conversion to contact pads after the device has been electrically characterized following burn-in. Furthermore, an adapter and a method for burn-in and testing are disclosed for use in testing a variety of different semiconductor devices. The adapter comprises a carrier having a pattern of testing pads bordering the carrier outline, and routing strips which are structured such that the carrier is adaptable to the package of the device being tested.

Semiconductor device testing and burn-in methodology

An integrated circuit package having a top opening and a cavity, with a chip adhered in the cavity. The top opening has routing strips electrically connecting the top opening with the outer surface. The routing strips are electronically connected to bonding pads located in a central area of the chip. Following assembly of the components, the top opening and the cavity are encapsulated in a molding process. A method is provided for forming a substantially flat integrated circuit package.

Integrated circuit package and flat plate molding process for integrated circuit package

A thin, stacked face-to-face integrated circuit packaging structure includes a chips attached to both major surfaces of a rigid interposer, and interconnected by printed wiring traces and vias to external solder ball contacts attached to the interposer.

Thin stacked integrated circuit device

A method and apparatus for producing an integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending into the opening (86), a plurality of pads (100) disposed on the first and second surfaces (92, 94) are electrically connected with at least one of the routing strips (82), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and a silicon chip (50) attached to the printed circuit board (70) by an adhesive material (60) that provide a seal between silicon chip (50) and printed circuit board (70) is disclosed.

Method for adhering and sealing a silicon chip in an integrated circuit

An integrated circuit package (30) comprising a substrate (70) having an opening (86) and first and second surfaces (92, 94), a plurality of routing strips (82) being integral with the substrate (70) and extending to opening (86), a plurality of pads (100) disposed on the first surface (92) and electrically connected with at least one of the routing strips (82), a chip (50) having bonding pads (120) is adhered to the second surface (84) of the substrate (70) and is of substantially the same outline as substrate (70), wire bonding (80) electrically connecting at least one bonding pad (120) to at least one of the routing strips (82) and potting material (90) filling the opening (86) is disclosed.

Chip size integrated circuit package

A lead (10) for a semiconductor device (12) comprising a strip portion (14) comprising a first substantially horizontal portion (18) connected to the semiconductor device (12), a substantially vertical portion (20) connected to the first substantially horizontal portion (18), and a second substantially horizontal portion (22) connected to the substantially vertical portion (20) with at least one hole (16) disposed in the strip portion (14). A method of providing an electrical contact for connecting a semiconductor device (12) to a surface (24) comprising the steps of extending at least one lead (10) from the semiconductor device (12) and slotting the lead (10).

Slotted lead for a semiconductor device

An integrated circuit package (30) including a substrate (70) having an opening (86) and first and second surfaces(92, 94), a plurality of pads (100) disposed on the first and second surfaces (92, 94) having disposed thereon solder balls (150) electrically connected by a via (84) that provides the end-user with flexibility in the location of a power supply Pin (96) is disclosed.

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Singapore, Singapore

Min Yu Chan