Samsung Electronics Co., Ltd.

Seoul National University

Min-Wook Ahn

Won-Sub Kim

Jin-Seok Lee

Tai-song Jin

Dong-Hoon Yoo

Hee-Jin Ahn

Bernhard Egger

Seung-won Lee

Chae-Seok Im

Yun-Heung Paek

Suk-jin Kim

Young-hwan Park

Ki-seok Kwon

Jun-Seo Lee

Jin-Sae Jung

Rakie Kim

Hee-jun Shim

Yen-Jo Han

Jun-sik Choi

Shin-gyu Kim

Jin-sae Jung

Doo-san Cho

Jin-oo Joung

Tai Song Jin

Jang-seop Shin

Kyung-Mok Kum

Keon-Cheol Shin

An electronic device may comprise: a first memory for storing first data at a designated rate; a first processor connected to the first memory and configured to divide the first data into multiple second data, each having a size smaller than the size of the first data; a second memory for storing at least some of the multiple second data at a rate faster than the designated rate; a second processor connected to the second memory and configured to process the at least some of the multiple second data; and a DMA control module, connected to the second processor, for transmitting/receiving data between the first memory and the second memory, wherein the DMA control module is configured to: at least on the basis of a processing command for the multiple second data which is transmitted from the first processor to the second processor, receive, from the first memory, the at least some of the multiple small-sized second data divided from the first data; transmit the at least some of the multiple second data to the second processor; and transmit, to the first memory, third data processed by the second processor by using the at least some of the multiple second data.

Method and electronic device for data processing between multiple processors

Provided is a data processing method including the operations of storing, in a register, a first immediate portion included in a first instruction, from among the first immediate portion and a second immediate portion that constitute an immediate value, which is an operand; determining the immediate value by catenating the second immediate portion included in a second instruction with the stored first immediate portion; and performing an operation by using a value indicated by the second instruction and the determined immediate value.

Method and device for processing an instruction having multi-instruction data including configurably concatenating portions of an immediate operand from two of the instructions

Provided is a modulo scheduling method. The modulo scheduling method includes conducting a search, based on a data dependency graph of a loop, for a recurrence in which a sum of iteration distances between command nodes is less than a predetermined critical value; and determining a processing order of the recurrence.

Method and apparatus for modulo scheduling

A command processing method and processor performing the method are provided. The method includes: determining a priority of a variable of a program based on a usage frequency of the variable; determining an address at which a value of the variable is stored in a memory based on the priority of the variable; and generating a command that relates to the variable based on a bit string length of the address.

Processor and command processing method performed by same

A method of generating a code for a remote procedure call (RPC) includes obtaining a source code including information indicating a part where the RPC is to be performed, and generating a code for calling the RPC and a code for executing an RPC procedure, by analyzing the source code including information indicating the part where the RPC is to be performed.

Method of generating automatic code for remote procedure call

A technology for executing an external operation from a software-pipelined loop is provided. Code performance efficiency can be improved by overlapping the execution of the external operations of the loop and the iterations of the loop.

Apparatus and method for executing external operations in prologue or epilogue of a software-pipelined loop

A modulo scheduling method including calculating at least two candidate initiation intervals between adjacent iterations, searching for schedules of the instructions in parallel by using the candidate initiation intervals, and selecting a schedule determined to be valid from among the searched schedules.

Method and apparatus of instruction scheduling using software pipelining

A method for scheduling loop processing of a reconfigurable processor includes generating a dependence graph of instructions for the loop processing; mapping a first register file of the reconfigurable processor on an arrow indicating inter-iteration dependence on the dependence graph; and searching for schedules of the instructions based on the mapping result.

Method and apparatus for instruction scheduling using software pipelining

An apparatus for detecting a source code error location in a mixed-mode program is disclosed. The apparatus may include a compiler, a mapping table generator, a simulator, a comparison data generator and an error location detector. The apparatus extracts low-level data while simulating a verification program and while simulating a reference program. The low-level data is mapped to mapping tables for a verification program and a reference program, and by comparing the tables it is determined if there is an error in the mixed-mode program and if so, where.

Apparatus and method for detecting location of source code error in mixed-mode program

A technique for minimizing overhead caused by copying or moving a value from one cluster to another cluster is provided. A number of operations, for example, a mov operation for moving or copying a value from one cluster to another cluster and a normal operation may be executed concurrently. Accordingly, access to a register file outside of the cluster may be reduced and the performance of code may be improved.

Apparatus and method for reducing overhead caused by communication between clusters

Provided are a reconfigurable processor, which is capable of reducing the probability of an incorrect computation by analyzing the dependence between memory access instructions and allocating the memory access instructions between a plurality of processing elements (PEs) based on the results of the analysis, and a method of controlling the reconfigurable processor. The reconfigurable processor extracts an execution trace from simulation results, and analyzes the memory dependence between instructions included in different iterations based on parts of the execution trace of memory access instructions.

Reconfigurable processor and method for processing loop having memory dependency

A reconfigurable processor which merges an inner loop and an outer loop which are included in a nested loop and allocates the merged loop to processing elements in parallel, thereby reducing processing time to process the nested loop. The reconfigurable processor may extract loop execution frequency information from the inner loop and the outer loop of the nested loop, and may merge the inner loop and the outer loop based on the extracted loop execution frequency information.

Reconfigurable processor and method for processing a nested loop

An apparatus and method for dynamically determining the execution mode of a reconfigurable array are provided. Performance information of a loop may be obtained before and/or during the execution of the loop. The performance information may be used to determine whether to operate the apparatus in a very long instruction word (VLIW) mode or in a coarse grained array (CGA) mode.

Apparatus and method for dynamically determining execution mode of reconfigurable array

A method to transfer a plurality of data stored in a memory using one instruction. In a memory including at least two regions to which the addresses are assigned respectively, data are allocated to the addresses in sequence, and the allocated data are transferred using one instruction. At least one block is generated, which transfers data using one instruction, and it is instructed to include the data in the at least one block. The data in the block are linked with each other, and the number of paths linking two data is calculated with respect to the at least one block. The data are linked using shortest paths in consideration of the number of the linking paths, and the data are allocated by the addresses using the shortest paths.

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Seoul, South Korea

Min-Wook Ahn