Samsung Electronics Co., Ltd.

Min-wk Hwang

Jae-Ho Kim

Hyun-Chul Kim

Won-mo Park

Won-cheol Hong

Hung-mo Yang

Won-taek Choi

A method of fabricating a semiconductor memory device includes preparing a semiconductor substrate which is divided into a cell array region and a core and peripheral region adjacent to the cell array region. Signal lines may be formed in a lower layer in a cell region. An insulation layer may be formed on the lower layer. Signal lines connected to cell region signal lines may be formed on an insulation layer of the peripheral region. A capping layer may be formed on the insulation layer and the core and peripheral signal lines. The capping layer may be etched to expose the lower layer of the cell array region and an etch stop may be formed on the lower layer and the core and peripheral region.

Method of fabricating and semiconductor memory device using the same

Methods of forming semiconductor devices containing field oxide and channel-stop isolation regions therein include the steps of forming a plurality of first channel-stop isolation regions by implanting first conductivity type impurities at a first dose level into a face of a semiconductor substrate and then forming respective field oxide isolation regions at the locations where the first channel-stop isolation regions have been implanted. A conductive layer, which contacts active regions of the substrate and covers the field oxide isolation regions, is then patterned over the field oxide isolation regions to expose central portions of the upper surfaces of the field oxide isolation regions. The patterned conductive layer constitutes a landing pad layer which is preferably used as a mask during the formation of second channel-stop isolation regions in the substrate, by implanting first conductivity type impurities through the exposed upper surfaces of the field oxide isolation regions, into the centers of the first channel-stop isolation regions. During this step, the impurities are implanted at a higher dose and energy level so that the first and second channel-stop regions collectively form T-shaped channel-stop regions underneath respective field oxide isolation regions, when viewed in transverse cross-section. By reducing the concentration of the channel-stop impurities near the edges of the field oxide isolation regions and active regions, leakage currents can be reduced and refresh characteristics of memory devices can be improved by reducing the strength of parasitic electric fields in the substrate. However, by maintaining relatively high concentrations of the channel-stop impurities under the center of the field oxide isolation regions, electrical isolation of adjacent devices can be maintained at high levels.

Methods of forming integrated semiconductor devices having improved

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Yongin-si, South Korea

Min-wk Hwang