Samsung Electronics Co., Ltd.

Industry-University Cooperation Foundation Hanyang University

Postech Research and Business Development Foundation

Min Tae Ryu

Min Hee Cho

Wonsok Lee

Sungwon Yoo

Minsu Lee

Kiseok Lee

Dongwook Kim

Jinkyu Kang

Hyun Chul Lee

Yongseok Kim

Yongjin Lee

Woo Bin Song

Hyoungwoo Choi

Ki Seok Lee

Min Su Lee

Jae Kyeong Jeong

Joonseon Jeong

Sang Hoon Uhm

Hyeon Joo Seul

Won Sok Lee

Huije Ryu

Daehoon Park

Hyomin Lee

Jae Seok Hur

Provided is a semiconductor memory device comprising a bit line extending in a first direction, a channel pattern on the bit line and including a first oxide semiconductor layer in contact with the bit line and a second oxide semiconductor layer on the first oxide semiconductor layer, wherein each of the first and second oxide semiconductor layers includes a horizontal part parallel to the bit line and first and second vertical parts that vertically protrude from the horizontal part, first and second word lines between the first and second vertical parts of the second oxide semiconductor layer and on the horizontal part of the second oxide semiconductor layer, and a gate dielectric pattern between the channel pattern and the first and second word lines. A thickness of the second oxide semiconductor layer is greater than that of the first oxide semiconductor layer.

Semiconductor memory device having a confinement layer with a two-dimensional electron gas in the confinement layer

Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a peripheral circuit structure including peripheral circuits on a semiconductor substrate and a first dielectric layer on the peripheral circuits, a cell array structure on the semiconductor substrate, and a shield layer between the peripheral circuit structure and the cell array structure. The cell array structure includes bit lines, first and second active patterns on the bit lines, first word lines that extend in a second direction on the first active patterns, second word lines that extend in the second direction on the second active patterns, data storage patterns on the first and second active patterns, and a second dielectric layer on the semiconductor substrate. A hydrogen concentration of the first dielectric layer is greater than that of the second dielectric layer.

Semiconductor memory device having shield layer between peripheral circuit and cell array structures

A porous composite structure including a substrate including a plurality of nanostructures; a particle layer disposed on a surface of the substrate; and a liquid, a method of preparing the porous composite structure, an article including the porous composite structure, and an air purifier including the porous composite structure.

Porous composite structure, method of preparing the same, article including the same, and air purifier including the same

A semiconductor memory device with improved performance by improving interface characteristics while reducing a leakage current, and a method for fabricating the same are provided. The semiconductor memory device includes a conductive line on a substrate, a first interlayer insulating layer exposing the conductive line and defining a channel trench on the substrate, a channel layer extending along a bottom and side surface of the channel trench, a first gate electrode and a second gate electrode spaced apart from each other in the channel trench, a first gate insulating layer between the channel layer and the first gate electrode, and a second gate insulating layer between the channel layer and the second gate electrode. The channel layer includes a first oxide semiconductor layer and a second oxide semiconductor layer sequentially stacked on the conductive line. The first oxide semiconductor layer has a greater crystallinity than the second oxide semiconductor layer.

Semiconductor memory device and method for fabricating the same

A semiconductor memory includes a bit line extending in a first direction, first and second active patterns, which are alternately disposed in the first direction and on the bit line, and each of which includes a horizontal portion and a vertical portion, first word lines disposed on the horizontal portions of the first active patterns to cross the bit line, second word lines disposed on the horizontal portions of the second active patterns to cross the bit line, and an intermediate structure provided in a first gap region between the first and second word lines or in a second gap region between the vertical portions of the first and second active patterns. The first and second active patterns, which are adjacent to each other, may be disposed to be symmetric with respect to each other.

Semiconductor memory device

Disclosed is a memory device including a row decoder generating word line (WL) control signals based on a row address from an external device, a first sub-array including memory cells connected to word lines, a first sub-word line driver (SWD) providing a selection voltage or a non-selection voltage to odd-numbered word lines of the word lines based on odd-numbered WL control signals corresponding to the odd-numbered word lines, and a second SWD providing the selection voltage or the non-selection voltage to even-numbered word lines of the word lines based on even-numbered WL control signals corresponding to the even-numbered word lines. The first SWD applies the non-selection voltage to non-selection word lines of the even-numbered word lines, in response to the even-numbered WL control signals, and the second SWD applies the non-selection voltage to non-selection word lines of the odd-numbered word lines, in response to the odd-numbered WL control signals.

Memory devices

Growing community of inventors

Hwaseong-si, South Korea

Min Tae Ryu