Skhynix Inc.

Min-Suk Lee

Jae-Heon Kim

Chan-Sik Park

Choi-Dong Kim

Jae-Hong Kim

Ki-Seon Park

Won-Joon Choi

Guk-Cheon Kim

Yang-Kon Kim

Jong-Koo Lim

Cha-Deok Dong

Bo-Mi Lee

Seung-Mo Noh

Jeong-Myeong Kim

Chang-Hyup Shin

Jung-Hwan Moon

June-Seo Kim

Bo-Kyung Jung

Ji-Hun Park

Methods, systems, and devices are disclosed for implementing semiconductor memory using variable resistance elements for storing data. In one aspect, an electronic device is provided to comprise a semiconductor memory unit including: a substrate; an interlayer dielectric layer disposed over the substrate; and a variable resistance element including a seed layer formed over the interlayer dielectric layer, a first magnetic layer formed over the seed layer, a tunnel barrier layer formed over the first magnetic layer, and a second magnetic layer formed over the tunnel barrier layer, wherein the seed layer includes a conductive material having a metallic property and an oxygen content of 1% to approximately 10%.

Electronic device and method for fabricating the same

Electronic devices and systems having semiconductor memory are provided. In one implementation, for example, an electronic device may include a substrate; an under layer disposed over the substrate and including conductive hafnium silicate; a free layer disposed over the under layer and having a variable magnetization direction; a tunnel barrier layer disposed over the free layer; and a pinned layer disposed over the tunnel barrier layer and having a pinned magnetization direction, and wherein the free layer includes: a first ferromagnetic material; a second ferromagnetic material having a coercive force smaller than that of the first ferromagnetic material; and an amorphous spacer interposed between the first ferromagnetic material and the second ferromagnetic material.

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes an interlayer dielectric layer formed over a substrate and having a contact hole; a lower contact filled in a part of the contact hole; and a variable resistance element which is disposed over and coupled to the lower contact, and has a first part filled in the contact hole and a second part disposed over the first part and protruding over the interlayer dielectric layer, wherein the first part includes a first metal which has a higher electron affinity than a component included in the second part, and an oxide of the first metal is an insulating material.

This technology provides an electronic device. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a contact plug; a first stack structure disposed over the contact plug and coupled to the contact plug, wherein the first stack structure includes a pinning layer controlling a magnetization of a pinned layer; and a second stack structure disposed over the first stack structure and coupled to the first stack structure, wherein the second stack structure includes a MTJ (Magnetic Tunnel Junction) structure which includes the pinned layer having a pinned magnetization direction, a free layer having a variable magnetization direction, and a tunnel barrier layer interposed between the pinned layer and the free layer, wherein a width of the first stack structure is larger than a width of the contact plug and a width of the second stack structure.

Electronic device including a semiconductor memory

In one implementation, an electronic device is provided to include a semiconductor memory, wherein the semiconductor memory may include: a variable resistance element including a Magnetic Tunnel Junction (MTJ) structure including a free layer having a changeable magnetization direction free layer, a pinned layer having a fixed magnetization direction and a tunnel barrier layer interposed between the free layer and the pinned layer, and the electronic device may further include, in a first direction in which the free layer, the tunnel barrier layer and the pinned layer are arranged, a first permanent magnet having a first surface facing a first surface of the variable resistance element and spaced from the variable resistance element, wherein a magnetic field generated by the first permanent magnet may have a direction which offsets or reduces an influence of a stray field generated by the pinned layer.

Electronic device

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a substrate; a plurality of variable resistance elements formed over the substrate and arranged as a matrix, spacer patterns formed over the substrate to surround the variable resistance elements in the matrix with a thickness sufficient to define contact holes between the variable resistance elements, and a source line contact buried in the contact hole.

A method of manufacturing an electronic device including a semiconductor memory is provided. The method may include forming a material layer for forming a variable resistance element over a substrate, forming a metal layer over the material layer, forming a mask pattern over the metal layer, forming a metal layer pattern by etching the metal layer using the mask pattern as an etch barrier, performing a surface treatment on the metal layer pattern, and etching the material layer using the metal layer pattern and the metal compound layer as an etch barrier to form a variable resistance element having an external side aligned with an external side of the metal compound layer. An external part of the metal layer pattern may be transformed into a metal compound layer. The metal compound layer may have a low etch rate as an etch barrier.

Method of manufacturing an electronic device including a semiconductor memory having a metal electrode and a metal compound layer surrounding sidewall of the metal electrode

An electronic device including a semiconductor memory is provided. The semiconductor memory includes an interlayer dielectric layer disposed over a substrate, and having a recess which exposes a portion of the substrate; a bottom contact partially filling the recess; and a resistance variable element including a bottom layer which fills at least a remaining space of the recess over the bottom contact, and a remaining layer which is disposed over the bottom layer and protrudes out of the interlayer dielectric layer.

This technology provides an electronic device and a method of fabricating the same. An electronic device in accordance with an implementation of this document includes semiconductor memory, and the semiconductor memory includes a lower electrode, a variable resistance element over the lower electrode, an upper electrode disposed over the variable resistance element and including metal, and a metal compound layer configured to surround a side of the upper electrode. The metal compound layer includes a compound of the metal of the upper electrode.

Growing community of inventors

Icheon-si, South Korea

Min-Suk Lee