Skhynix Inc.

Lg Electronics Inc.

Korea Institute of Science and Technology

Min Su Park

Man Tae Hwang

Hoi Kil Jeong

Jin Young Kim

Young Bok Son

Jae Kyum Kim

Chang Hoon Lee

Sung Hwa Lee

Kie Tak Hyun

Kyeong Seon Jeong

Gun Ho Ha

Jin Wook Seo

Moo Hyun Ko

Hae Seock Yang

Chang Ho Yun

Jin Hyouk Shin

Myung Sig Yoo

Jong Su Choo

Il Joong Kim

Yun Hee Park

Dong Kyun Kim

Geun Ho Choi

Young Jun Ku

Dong Uk Lee

Jae Il Kim

Hak Song Kim

Hyuk-Min Kwon

Joo Young Kim

Ji Hyun Kim

Kyung Jin Kim

Yong Sang Park

Min Soo Lim

Jung Ah Hwang

Yong Chae Jung

Cheol-Min Yang

Junyeon Hwang

Yong Man Park

Jee Young Chun

Sae Kyu Park

Min Gyu Park

Hang Ah Jo

Eun Sil Lee

Hoon Moo Choi

Young Ho Kim

Ji Young Kim

Sang-Soo Lee

Sang Sic Yoon

Eun Seok Choi

Won Jun Choi

Sun Myung Choi

Heesuk Kim

Jin Hee Cho

Sanghyeon Kim

Jeong Gon Son

Seung Wook Oh

Jong Hyuk Park

Seungjun Chung

Sang Hyun Ku

Jung Bae Hwang

Jin Il Chung

Tae Ann Kim

Han Kyu Chi

Hong Gyeom Kim

Yu Ri Lim

Jae Ho Choi

Sang Hyun Lee

Youngpyo Ko

Young Mok Jeong

Young-Gun Min

Jaesang Yu

Ji Hye Hwang

Hun-su Lee

Mi Sun Hwang

Daun Lim

Seong Yun Kim

Daemyeong Geum

Hye Jin Yoo

Hae Rim Park

Myung Sig Lg Electronics Chanagwon 1St Factory Yoo

Young Ho Lg Changwon 1 Factory Kim

Young Ho Lg Electr Senghwalgwan Kim

A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Memory device, semiconductor system, and data processing system

A semiconductor device includes an alignment data generation circuit aligning first and second latch data generated from a first group of input data in synchronization with a first internal strobe signal, outputting the aligned first and second latch data as first alignment data, aligning a first and second latch data generated from a second group of the input data in synchronization with a second internal strobe signal, and outputting the aligned first and second latch data as second alignment data. The semiconductor device includes a write data generation circuit generating first and second write data from the first and second alignment data in synchronization with a latch clock after the start of a first operation mode and generating the first and second write data from the first alignment data in synchronization with the latch clock after the start of a second operation mode.

Semiconductor device for performing data alignment operation

A memory may include multiple rows each coupled to multiple memory cells; a target row classification circuit suitable for classifying, as a target row, a row, among the multiple rows, that is susceptible to data loss as a result of activity of an adjacent row; and a target row signal generation circuit suitable for sequentially activating a target row active signal for activating the target row and a target row precharge signal for precharging the target row in response to a precharge command.

Memory with capability to detect rows that are prone to data loss, memory system and operation method of memory

A conductive polymer composite for adhesion to a flexible substrate contains a polymer adhesive containing a curable polymer and a curing agent; and a conductive filler containing a metal and a carbonaceous material dispersed in the polymer adhesive. The conductive polymer composite is suitable for application to not only the human body but also other objects having irregular surface. In addition, due to enhanced adhesive strength of the conductive polymer composite to the flexible substrate, the reduction in conductivity or conductivity breakdown caused by external stress can be prevented and flexibility and stretchability can be improved.

Conductive polymer composite for adhesion to flexible substrate and method for preparing same

An electronic device includes an enable signal generation circuit configured to activate, when a write operation is performed, a termination enable signal earlier than a time point when a write latency elapses, by a duration amount of an entry offset period; and a data input and output circuit configured to receive, when the write operation is performed, data later than the time point when the write latency elapses, based on the termination enable signal, wherein the data input and output circuit receives the data after the write latency elapses by a duration amount of a first data reception delay period.

Electronic device and electronic system related to performance of a termination operation

A semiconductor system includes a semiconductor device and a controller. The semiconductor device includes a first memory rank and is configured to perform, in response to receiving a first write command, a first write operation of writing first data to the first memory rank. The semiconductor device includes a second memory rank and is configured to perform, in response to receiving a second write command, a second write operation of writing second data to the second memory rank. The controller is configured to receive at least one write request and responsively generate the first and second write commands separated in time so that a transition time interval between generation of the first write command and generation of the second write command is based on the second memory rank being different from the first memory rank and based on a comparison of a write preamble period to a write post-amble period.

Methods, controllers, and semiconductor systems for generating write commands

A semiconductor device includes an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit is configured to generate an internal command pulse based on a write signal, a latency code, and an offset code. The sense data generation circuit is configured to generate a sense data based on the internal command pulse and an internal data strobe signal and configured to generate the sense data based on the internal command pulse and a delayed strobe signal.

Semiconductor devices performing a write leveling training operation and semiconductor systems including the semiconductor devices

A system for performing a phase matching operation includes a controller configured to output a dock, a command, and a strobe signal, and to input/output data. The system also includes a semiconductor device configured to generate an internal strobe signal by matching the phases of the command and the strobe signal according to the clock, and to input/output the data in synchronization with the internal strobe signal, wherein the semiconductor device generates the internal strobe signal from the strobe signal by compensating for a delay amount of a first path to which the command is inputted and a delay amount of a second path to which the strobe signal is inputted.

System for performing phase matching operation

A semiconductor apparatus may be provided. The semiconductor apparatus may include a fine training circuit configured to generate a fine result signal based on a clock signal, a data strobe signal, and a command. The semiconductor apparatus may include a coarse training circuit configured to generate a coarse result signal based on the clock signal, the data strobe signal, and the command and to set an offset of a write enable signal based on an offset control signal.

Semiconductor apparatus, semiconductor system, and training method

A method includes performing a first write leveling training operation and performing a second write leveling training operation. The first write leveling training operation is performed to generate transmission data based on a data strobe signal and an internal command pulse and to generate a latency code. The second write leveling training operation is performed to generate the transmission data based on the data strobe signal and the internal command pulse.

A semiconductor device may include an internal command pulse generation circuit and a sense data generation circuit. The internal command pulse generation circuit may generate an internal command pulse from a write signal based on an offset code and an internal clock signal. The sense data generation circuit may generate sense data from an internal data strobe signal based on the internal command pulse. The internal command pulse may be generated by delaying the write signal by a shift period based on the internal clock signal. The shift period may be controlled by the offset code.

Semiconductor device and semiconductor system including the semiconductor device for aligning an internal data strobe signal using an offset code

A semiconductor device includes a shift register and a control signal generation circuit. The shift register generates shifted pulses, wherein a number of the shifted pulses is controlled according to a mode of a burst length. The control signal generation circuit generates a control signal for setting a burst operation period according to a period during which the shifted pulses are created. The burst operation period is a period during which a burst operation is performed.

Semiconductor devices

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Seoul, South Korea

Min Su Park