Samsung Electronics Co., Ltd.

Lg Display Co., Ltd.

Samsung Display Co., Ltd.

Skhynix Inc.

Hyundai Motor Company

Kia Motors Corporation

Hynix Semiconductor Inc.

Samsung Mobile Display Co., Ltd.

Avago Technologies International Sales Pte. Limited

Kyungpook National University Industry-academic Cooperation Foundation

Koh Young Technology Inc.

Kumho Electric Inc.

Min-Su Kim

Dae-Seong Lee

Hyun-chul Hwang

Dong-Su Yee

Chan-Kyoung Moon

Dai-Han Cho

Jong-Kyu Ryu

Hyun-Hee Lee

Chung-Hee Kim

Ji-Kyum Kim

Ah-Reum Kim

Hyun Shik Lee

Chan-Hee Wang

Jong-Woo Kim

Matthew S Berzins

Tae-Keun Lee

Se-Hwan Kim

Hae-Jun Park

Young-Taek Hong

Jin-Soo Park

Seung-Bum Kim

Uk-Rae Cho

Hyung-Gon Kim

Jung-Ho Hwang

Gun-Ok Jung

Deok-Woo Lee

Ju-Hyun Kang

Rahul Singh

Seung-beom Park

Kwang-Hyun Kim

Chul-Woo Park

Kuen-Dong Ha

Beong-hun Beon

Bai-Sun Kong

Na-Young Shin

Gwan-Young Na

Young-Hoon Shin

Sung-Wook Chang

Kyu-Hyeong Cheon

Jin-Su Park

Yun-Hui Han

Hyoung-Wook Lee

Kyu-Seob Han

Neung-Hee Lee

Tae-Hyeok Kang

Myeong-Sik Lee

Yong-Geol Kim

Kwan-Hee Lee

Hyun Woo Lee

Seung-Yong Song

Tae-Hyung Kim

Kyung-Ho Park

Prashant U Kenkare

Young-Seo Choi

Oh-June Kwon

Chi-Hyun Cho

Seung-Chul Choi

Ji-hoon Kim

Junghoon Park

Sun-Young Jung

Jinman Han

Sangwan Nam

Byung-Sun Kim

Jae-Woo Seo

Ji-Hun Ryu

Jae-Yong Kim

Young-Cheol Joo

Hee-Sung Kang

Sung-Woo Park

Young-Gun Ko

Sung-Joon Kim

Kwang-Hee Lee

Sun-Hwa Kim

Jong Chan Lee

Young-wug Kim

Hyun-Min Hwang

Yong-Jin Yoon

Jung-Jun Im

Namsoo Kim

Kwang-Il Kim

Sang-Seon Lee

Hyun-Sung Lee

Hyoung Wook Lee

Byoung-Ho Kim

Ho-Chul Lee

Hyun Hee Lee

Seung-Wook Nam

Jong-Bok Kim

Min-Young Kim

Ji-Ho Kang

Dae-young Moon

James Jung Lim

So-Ra Park

Byoung-June Lee

Taek-Joon Lee

Ja-Geun Kim

Seung-Chul Lee

Sang-shin Han

Weon-ho Park

In-Soo Lee

An integrated circuit including first and second macroblocks arranged in a first direction, and a plurality of cells between the first macroblock and the second macroblock, the plurality of cells including at least one first ending cell adjacent to the first macroblock and having a first width in the first direction, at least one second ending cell adjacent to the second macroblock and having a second width different from the first width in the first direction, and at least one standard cell between the at least one first ending cell and the at least one second ending cell may be provided.

Integrated circuit including asymmetric ending cells and system-on-chip including the same

A gate driver includes a first scan signal generator configured to output a logic voltage for driving of a scan transistor through a plurality of stages connected in cascade, the scan transistor performing a switching operation to transfer a data voltage to a driving transistor of a pixel, a second scan signal generator configured to output a logic voltage for driving of a sensing transistor through the plurality of stages, the sensing transistor sensing deterioration of a light emitting element of the pixel, a light emission control signal generator configured to output a logic voltage for control of a light emission control transistor of the pixel through the plurality of stages, and an initialization voltage generator driven by logic voltages received from some nodes of the first scan signal generator based on the light emission control signal generator to supply an initialization voltage to the pixel.

Gate driver and organic light emitting display device including the same

Provided are semiconductor circuits. A semiconductor circuit includes a first circuit configured to propagate a value of a first node to a second node based on a voltage level of a clock signal; a second circuit configured to propagate a value of the second node to a third node based on the voltage level of the clock signal; and a third circuit configured to determine a value of the third node based on a voltage level of the second node and the voltage level of the clock signal, wherein the first circuit comprises a first transistor gated to a voltage level of the first node, a second transistor connected in series with the first transistor and gated to the voltage level of the third node, and a third transistor connected in parallel with the first and second transistors and gated to a voltage level of the clock signal to provide the value of the first node to the second node.

Clock gating circuit

A semiconductor device is provided. The semiconductor device includes a first hard macro; a second hard macro spaced apart from the first hard macro in a first direction by a first distance; a head cell disposed in a standard cell area between the first hard macro and the second hard macro, the head cell being configured to perform power gating of a power supply voltage provided to one from among the first hard macro and the second hard macro; a plurality of first ending cells disposed in the standard cell area adjacent to the first hard macro; and a plurality of second ending cells disposed in the standard cell area adjacent to the second hard macro, the head cell not overlapping the plurality of first ending cells and the plurality of second ending cells.

Semiconductor devices, methods of designing layouts of semiconductor devices and methods of fabricating semiconductor devices

An electronic device is provided. The electronic device includes a battery, a power management integrated circuit (PMIC), that is electrically connected to the battery, adjusts at least part of power received from the battery, and outputs a controlled power, a processor electrically connected to the PMIC, at least one power sensor that is one of electrically connected between the battery and the PMIC and constitutes a part of the PMIC, and a control circuit electrically connected to the at least one power sensor. The control circuit acquires at least one of a current value and a power value input into the PMIC from the battery, determines whether at least one of the acquired current value and power value is greater than or equal to a threshold, and generates a first signal for controlling at least one of the PMIC and the processor, at least partially based on the determination.

Electronic device for managing power and method of controlling same

A touch display device for preventing the occurrence of a short circuit between routing lines is disclosed. The touch display device includes a dam forming a boundary with an encapsulation unit covering a light-emitting element, and the dam is formed such that the height thereof in a region that overlaps routing lines, which are connected to touch electrodes disposed on the encapsulation unit, and the height thereof in a region that does not overlap the routing lines are different from each other, thereby preventing the occurrence of a short circuit between the routing lines.

Touch display device

A memory device includes: a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

Memory device having improved data reliability by varying program sequences

A memory device includes a plurality of latches arranged in a plurality of columns including a first column and a second column and in a plurality of rows, a first flip flop configured to output first data, to first latches arranged in the first column, among the plurality of latches, based on a clock, and a second flip flop configured to output second data, to second latches arranged in the second column, among the plurality of latches, based on the clock. The first flip flop is further configured to, in a lock time section in which the first latches and the second latches maintain an output regardless of an input, block output of the first data to the first latches, and the second flip flop is further configured to, in the lock time section, block output of the second data to the second latches.

Memory device including plurality of latches and system on chip including the same

A memory device includes: a memory cell region; a peripheral circuit region; a memory cell array; a control logic circuit; and a row decoder. The row decoder is configured to activate string selection lines based on control of the control logic circuit. A program interval is formed between a first program operation and a second program operation. The control logic circuit includes a reprogram controller configured to control the row decoder so that a program interval differs in the memory cells connected to different string selection lines among the memory cells connected to a first wordline.

Three-dimensional NAND flash memory device having improved data reliability by varying program intervals, and method of operating the same

An integrated circuit including standard cells, a method and a computing system for designing and fabricating the same are provided. A computer-implemented method involves placing, based on a standard cell library, standard cells of an integrated circuit to be fabricated, and routing the placed standard cells. A position of a first wiring of a placed cell among the placed standard cells may be adjusted based on a position of a second wiring used for the routing. The first wiring is provided from at least one standard cell, formed in a same layer as that of the second wiring, and spaced from the second wiring in a first direction. An integrated circuit layout having the adjusted position of the first wiring, is produced.

Integrated circuit including standard cell and method and system for designing and manufacturing the same

Growing community of inventors

Hwaseong-si, South Korea

Min-Su Kim