Skhynix Inc.

Min Su Choi

Dae Sung Kim

Jae Yong Son

Provided herein may be a memory controller and a memory system including the same. The memory controller may include an error correction circuit configured to perform error correction decoding on data that is read by read retry operations, a buffer memory configured to store decoding history information including retry fail voltages used for a failure in the read retry operations and syndrome weights respectively corresponding to the retry fail voltages, and a processor configured to, when a number of times that the read retry operations fail reaches a threshold number of times, determine a voltage corresponding to a minimum syndrome weight determined based on a relationship between changes in the syndrome weights relative to magnitudes of the retry fail voltages, to be an optimally estimated read voltage, and provide data that is read using the optimally estimated read voltage to the error correction circuit.

Memory controller and memory system including the same

A memory device may include a read controller and an error correction circuit. The read controller may sequentially perform a plurality of read retry operations on a memory device. The error correction circuit may perform a plurality of first error correction decodings on read data respectively acquired from the plurality of read retry operations, store a plurality of Unsatisfied Syndrome Check (USC) values respectively produced by the plurality of first error correction decodings, and perform a second error correction decoding based on read data corresponding to a minimum USC value among the plurality of USC values.

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Icheon, South Korea

Min Su Choi