Skhynix Inc.

Min Soo Lim

Yong Sang Park

Joo Young Kim

Min Su Park

Dae Woo Kim

Young Duke Seo

A memory device includes a memory cell array and a peripheral circuit. The memory cell array includes a plurality of memory regions each identified by a row address and a column address. The peripheral circuit accesses the memory cell array by performing, based on an address, a burst length and a burst address gap provided from a memory controller, a burst operation supporting a variable burst address gap. The burst address gap is a numerical difference between adjacent column addresses, on which the burst operation is to be performed.

Memory device, semiconductor system, and data processing system

A data processing system may be configured to include a memory device, a controller configured to access the memory device when a host requests offload processing of an application, and process the application, and a sharing memory management component within the controller and configured to: set controller owning rights of access to a target region of the memory device in response to the host stores, in the target region, data used for the requested offload processing of the application; and set the controller owning rights of access or the host owning rights of access to the target region based on a processing state of the application.

Data processing system and operating method thereof

A data bus inversion (DBI) circuit of a memory device includes a first processing component configured to generate first combination data by combining read data read from a memory cell region and previous data previously outputted from a data line, and generate second combination data by selectively inverting the first combination data depending on a result of comparing the first combination data and the previous data; and a second processing component configured to generate data to be outputted from the data line, by combining the second combination data and the previous data, wherein the second processing component generates bits of unnecessary bit positions in the data to be the same as bits of the unnecessary bit positions in the previous data.

DBI circuit and memory device including the same

The present disclosure relates to a memory system and an operating method thereof. The memory system may include a shared memory device to store data, a sharing manager to store operation policy information and to autonomously generate a first internal command by using the operation policy information during an auto mode started in response to receiving an auto mode start command from a host, and a memory controller to generate a second internal command for controlling the shared memory device in response to the first internal command.

Memory system and operating method of a memory system

A memory system includes a memory group including a plurality of memory devices having two or more different types; and a controller configured to control data input and output for the memory group, wherein the controller includes a scrubbing controller configured to collect health information to which a deterioration degree for each of the plurality of memory devices is reflected and determine a scrubbing interval for each of the plurality of memory devices based on the health information, the scrubbing interval being reduced in proportion to the deterioration degree.

Growing community of inventors

Hwaseong-si, South Korea

Min Soo Lim