Samsung Electronics Co., Ltd.

Min-Soo Cho

Jin-Woo Kim

Dong-jun Kim

Dai-Geun Kim

Eui-Youl Ryu

Yong-Kyu Lee

Dong-Jun Kim

Jin-ho Kim

Weon-Ho Park

Chil-Hee Chung

Jeung-Wook Han

Jae-Hyun Park

Jin-Ho Kim

Kyung-Hyun Kim

Sang-Wook Park

Sang-rok Hah

Chul-soon Kwon

Dong-Jin Keum

Jae-Min Yu

Don-Woo Lee

Jeong-Lim Nam

Yong-Hee Kim

Young-Hee Kim

Il-Young Sohn

Ryotaro Kudo

Kook-Min Kim

Kwang-Bok Kim

Jae-Yeol Han

Joo-Chan Kim

Sag-Wook Park

Dai-Goun Kim

A buck-boost converter includes: a converting circuit; a ripple injector; a hysteresis comparator; and a switching controller. The converting circuit is configured to generate an output voltage by adjusting an input voltage in a buck mode, a boost mode, and a buck-boost mode. The ripple injector is configured to generate a ripple based on switching signals corresponding to switching operations of the converting circuit. The hysteresis comparator outputs at least one switching control signal by comparing an output control voltage with a feedback voltage generated by adding the ripple to a divided voltage generated by performing a voltage division on the output voltage. The switching controller is configured to change a current flow path of the converting circuit based on the at least one switching control signal.

Buck-boost converters and power management integrated circuits including the same

A negative level shifter includes a voltage selection unit and at least one voltage level conversion unit. The voltage selection unit may apply a first voltage to a first node and a second voltage to a second node if the control signal CON is the first value and apply a third voltage to the first node and a fourth voltage to the second node if the control signal CON is the second value. The at least one voltage level conversion unit may be connected to the first node and the second node and convert a voltage level of an input signal by using a voltage of the first node and a voltage of the second node.

Negative level shifters

Nonvolatile memory cells having a split gate structure and methods of fabricating the same are provided. The nonvolatile memory cells include active regions defined at a predetermined region of a semiconductor substrate. A portion of each of the active regions is etched to form a cell trench region. Insulated floating gates are disposed on a pair of sidewalls parallel with the direction that crosses the active region. A source region is disposed at a bottom surface of the cell trench region. A gap region between the floating gates is filled with a common source line electrically connected to the source region. The common source line is extended along the direction that crosses the active regions. The active regions, which are adjacent to the floating gates, are covered with word lines parallel with the common source line. Drain regions are disposed in the active regions adjacent to the word lines. The drain regions are electrically connected to bit lines that cross over the word lines.

Nonvolatile memory cells having split gate structure and methods of fabricating the same

EEPROM devices may be fabricated by forming a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer on an integrated circuit substrate, and a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and beneath a portion of the gate insulating layer. A first conductive layer, an interlevel insulating layer and a second conductive layer are sequentially formed on the tunnel insulating layer and on the gate insulating layer. The second conductive layer, the interlevel insulating layer and the first conductive layer then are patterned, to define a sense transistor gate on the tunnel insulating layer and on the gate insulating layer that comprises a first portion of the first conductive layer, a first portion of the interlevel insulating layer and a first portion of the second conductive layer, and to further define a select transistor gate on the gate insulating layer and spaced apart from the sense transistor gate, that comprises a second portion of the first conductive layer, a second portion of the interlevel insulating layer, and a second portion of the second conductive layer.

Methods of fabricating electrically erasable programmable read-only memory (EEPROM) devices including multilayer sense and select transistor gates

In a non-volatile semiconductor memory device and a fabrication method thereof, a charge storage layer is formed on a substrate. A control gate layer is formed on the charge storage layer. A gate mask having a spacer-shape is formed on the control gate layer. The charge storage layer and the control gate layer are removed using the gate mask as protection to form a control gate and a charge storage region.

Semiconductor device having a flash memory cell and fabrication method thereof

The method of manufacturing a split gate flash memory device includes the steps of (a) providing a semiconductor substrate of a conductivity type opposite to that of a first junction region; (b) sequentially forming a first dielectric film, a first conductive film, a second dielectric film and a third dielectric film on an overall upper face of the substrate; (c) etching the third dielectric film by a given thickness so as to expose the second dielectric film; (d) removing the exposed second dielectric film, and eliminating the remaining third dielectric film; (e) etching the first conductive film and the second dielectric film by a given thickness so as to partially expose the first conductive line and the first conductive film; (f) forming a fourth dielectric film on a portion of the exposed first conductive line and first conductive film; (g) eliminating the remaining second dielectric film remained, and exposing the first conductive film provided in a lower part thereof; and (h) etching the first dielectric film and the first conductive film exposed by the removal of the second dielectric film using the fourth dielectric film as an etch mask, and forming a second gate dielectric film and a word line.

Method of manufacturing split gate flash memory device

The present invention provides a method of forming a split gate type flash memory. After exposure of a floating gate layer between silicon nitride layers, a conductive layer spacer is formed on a sidewall of the silicon nitride layer pattern. The conductive layer spacer is formed in a floating gate of a later-completed flash memory to form a tip on which tunneling is centralized in an erase operation. That is, the spacer is formed on a sidewall of the silicon nitride layer pattern over the floating gate layer to form the tunneling tip.

Method of forming flash memory

A method for performing an erase operation in a memory cell. A first voltage and a second voltage are applied to the source and drain regions, respectively, for a predetermined erase time; and the first and second voltages are switched with each other between the source and drain regions at least one time for the erase time. Thereby, hole is easily injected to the source and drain regions and a channel lateral surface, and a uniform and high-speed erase operation is archived.

Erasing method in non-volatile memory device

In a method for manufacturing a flash memory device, a first gate insulating film, a first gate conductive film, and a second insulating film are sequentially formed on a semiconductor substrate. A region where a first gate is to be formed is defined by etching the second insulating film to expose an upper portion of the first gate conductive film. Second conductive film spacers are formed along sidewalls of the etched second insulating film. An oxide film is formed on the exposed surface of the second conductive film spacers and the first gate conductive film. Silicon insulating spacers are formed on the sidewalls of the etched second insulating film. A source junction contact hole is formed by etching the first gate conductive film and the first gate insulating film by using the second insulating film and the silicon insulating film spacers as a mask. A source junction contact fill is formed filling the source junction contact hole. The first gate is formed by sequentially removing the second insulating film and the first gate conductive film.

Method for manufacturing flash memory device

Disclosed is a method of planarizing a non-volatile memory device. After forming a floating gate structure on a cell area of a semiconductor substrate, a conductive layer, a hard mask layer and a first insulating layer are sequentially formed on the entire surface of the resultant structure. After removing the first insulating layer of the cell area to leave a first insulating layer pattern only on the peripheral circuit area, the hard mask layer of the cell area is removed. A second insulating layer is formed on the conductive layer and the insulating layer pattern to increase the height of the insulating layer on the peripheral circuit area. The second insulating layer and the first insulating layer pattern are removed until the floating gate structure is exposed, thereby planarizing the cell area and the peripheral circuit area. The conductive layer is patterned to form wordlines on both sidewalls of the floating gate structure and simultaneously, to form a gate of a logic device on the peripheral circuit area. When a CMP process for forming the wordline is carried out, the excessive polishing of the cell area adjacent to the peripheral circuit area can be prevented.

Method of planarizing non-volatile memory device

EEPROM devices include a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer, on an integrated circuit substrate, and a sense transistor gate on the tunnel insulating layer and on the gate insulating layer. The sense transistor gate includes a floating gate on the tunnel insulating layer and on the gate insulating layer, a first interlevel insulating layer on the floating gate opposite the tunnel insulating layer and the gate insulating layer, and a sense gate on the first interlevel insulating layer opposite the floating gate. A select transistor gate also is included on the gate insulating layer and spaced apart from the sense transistor gate. The select transistor gate includes a first select gate on the gate insulating layer that is spaced apart from the sense transistor gate, a second interlevel insulating layer on the first select gate opposite the gate insulating layer, and a second select gate on the second interlevel insulating layer opposite the first select gate that is spaced apart from the sense gate. A first doped region is beneath the tunnel insulating layer and extends to beneath the select transistor gate. A second doped region is beneath the sense transistor gate and is spaced apart from the first doped region. A third doped region is beneath the select transistor gate and is spaced apart from the first doped region. EEPROM devices may be fabricated by forming a gate insulating layer and a tunnel insulating layer that is thinner than the gate insulating layer on an integrated circuit substrate, and a first doped region in the integrated circuit substrate beneath the tunnel insulating layer and beneath a portion of the gate insulating layer. A first conductive layer, an interlevel insulating layer and a second conductive layer are sequentially formed on the tunnel insulating layer and on the gate insulating layer. The second conductive layer, the interlevel insulating layer and the first conductive layer then are patterned, to define a sense transistor gate on the tunnel insulating layer and on the gate insulating layer that comprises a first portion of the first conductive layer, a first portion of the interlevel insulating layer and a first portion of the second conductive layer, and to further define a select transistor gate on the gate insulating layer and spaced apart from the sense transistor gate, that comprises a second portion of the first conductive layer, a second portion of the interlevel insulating layer, and a second portion of the second conductive layer.

Growing community of inventors

Seongnam, South Korea

Min-Soo Cho