Fairchild Camera and Instrument Corp.

Min-Siu Huang

Nabil G Damouny

Yeshayahu Mor

Dan Wilnai

A microprocessor with a multiplexer having its output coupled to the input of the instruction register for storing instructions to be executed and applying the bits of the instruction as the input signals to a mapping PLA. The inputs of the multiplexer are the information bus coupled to external pins to receive instructions either from external memory or from an external console, and the output of the ALU. The path from the output of the ALU to the input of the instruction register allows better self testing of the processor by iteself and self-generation of input/output instructions. This structure simplifies the processor by allowing console requests, instructions from memory and self generated instructions all to be stored in the same register, i.e., the instruction register, thereby eliminating the need for separate registers for each type of instruction. Further, this structure simplifies programming of repetitive I/O instructions for polling large numbers of I/O devices having sequential addresses in memory mapped I/O applications. That is, the microprocessor has the capability of generating its own I/O instructions from an operand coming in from memory such as by adding it to the contents of an index register and supplying the result to the instruction register through the ALU output, the ALU bus, and the multiplexer as the address of the particular I/O device to read from or write to.

Microprocessor with compact mapped programmable logic array

A microprocessor data processing system (1700) includes system units (50, 1704) connected to a bus (1702), with a bus arbiter (1712) and a protocol for assigning bus access to the system units (50, 1704). The microprocessor (50) executes both arithmetic operations and floating point operations. A microcontrol store (162) stores common instructions usable in different floating point operations. A PLA (180) supplies addresses to microcontrol store (162) and provides a signal indicating floating point instruction type. The microprocessor (50) includes a pending interrupt register (250) connected to mask and enable logic (268). The mask and enable logic (268) is connected to a priority encoder (278), which is connected to an interrupt latch (282). The latch (282) supplies outputs to generate a current state storage address. Branch control logic (1938) receives branch conditions inputs and branch control information and generates control signals for a next micro address multiplexer (1934) in a pipelined instruction path.

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Mountain View, CA, United States of America

Min-Siu Huang