Skhynix Inc.

Min Sik Han

Byung Kuk Yoon

Jin Il Chung

Hong Gyeom Kim

Sung Chun Jang

Dae Ho Ra

A semiconductor device includes an internal clock generation circuit and a data processing circuit. The internal clock generation circuit delays first to fourth division clock signals, which are generated by dividing a frequency of a clock signal, by a delay time adjusted based on a first code signal and a second code signal to generate first to fourth internal clock signals. The data processing circuit aligns internal data in synchronization with the first to fourth internal clock signals to generate output data. The data processing circuit also interrupts generation of the output data based on first and second command blocking signals according to a point in time when a read command is inputted.

Semiconductor device performing duty ratio adjustment operation

A semiconductor device includes a latch control circuit configured to generate a latch input signal, which is enabled in response to a latency signal, and configured to generate a latch output signal, which is enabled in response to an order control signal. The semiconductor device also includes a pipe latch circuit configured to latch input data in response to a pipe input signal and configured to output the latched input data as latch data in response to a pipe output signal. The semiconductor device additionally includes a data output circuit configured to latch the latch data in response to the latch input signal and configured to output the latched latch data as output data in response to the latch output signal, wherein the output data is outputted by performing an alignment operation for the latch data in response to the latch output signal.

Semiconductor device

A semiconductor device includes a first termination circuit comprising an impedance value and configured to control the impedance value of the first termination circuit based on a first selection termination control signal and a termination control signal and a second termination circuit comprising an impedance value and configured to control the impedance value of the second termination circuit based on a second selection termination control signal and the termination control signal.

Semiconductor devices

A semiconductor device may be provided. The semiconductor device may include a first oscillation signal generation circuit for generating a first oscillation signal. The semiconductor device may include a second oscillation signal generation circuit for generating a second oscillation signal. The second oscillation signal generation circuit may be provided with a test voltage. The test voltage may be generated based on a burn-in test signal.

Semiconductor device and system relating to the reduction of test time in a ring oscillator burn-in test

A semiconductor test device and a semiconductor test method are disclosed. A semiconductor test device may include a DQ signal receiver, a test mode register set signal processor, and a test mode command generator. The DQ signal receiver may receive a first DQ signal through a first DQ pin. The test mode register set signal processor may receive a test mode register set signal in response to the first DQ signal, and may output a test mode register set pulse signal. The test mode command generator may generate a test mode command corresponding to an input address in response to the test mode register set pulse signal.

Semiconductor test device and semiconductor test method

A semiconductor device includes a division period signal generation circuit and a clock sampling circuit. The division period signal generation circuit generates a division period signal which is enabled in synchronization with a write period that is set according to a write command and latency information. The clock sampling circuit samples an internal strobe signal to output a sampling clock signal in response to the division period signal and the internal strobe signal during a sampling period. The sampling period is set to be longer than the write period.

Semiconductor devices and semiconductor systems including the same

A phase splitter includes: a first signal path; and a second signal path, wherein the phase splitter outputs an internal signal of the first signal path as a first phase signal, and mixes an output signal of the first signal path with an output signal of the second signal path, thereby outputting a second phase signal having a predetermined phase difference from the first phase signal.

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Icheon-si, South Korea

Min Sik Han