Marvell International Limited

Sandisk Technologies Inc.

Marvell Asia Pte., Ltd.

Parade Technologies, Ltd.

Marvellworld Trade Ltd.

Min She

Qiang Tang

Ken Liao

Yan Li

Runzi Chang

Siu Lung Chan

Kwang-Ho Kim

Chih-Hsin Wang

Kochung Lee

Hongquan Wang

Zhendong Guo

Yuanping Chen

YingFan Lee

Mengchuan Gao

An electronic device (e.g., a CTLE circuit of a receiver of a data link) includes a current source and two differential transistor groups. The current source is configured to generate a bias current according to a data rate of data carried by a pair of differential input signals. A subset of the two differential transistor groups is configured to be driven by the bias current to generate a pair of differential output signals from the pair of differential input signals. The two differential transistor groups include a first plurality of transistors receiving a first input signal and a second plurality of transistors receiving a second input signal. The first and second input signals form the pair of differential input signals. In some implementations, each transistor is coupled to a biasing circuit including a DC path coupled to an adjustable biasing voltage level for selecting and deselecting the respective transistor.

Continuous time linear equalizers (CTLEs) of data interfaces

A driver device of a data interface includes an input/output (I/O) interface, a power interface, a transmitter circuit, and a switching unit. The I/O interface is configured to couple to a load device. The power interface is configured to provide a power supply for transmitting data via the I/O interface. The transmitter circuit is coupled to the I/O interface and to the power interface and is configured to be powered by the power supply and provide an output signal to the load device via the I/O interface in a transmitter mode. The switching unit is coupled to the power interface and is configured to switch off the power interface for the transmitter circuit when the transmitter circuit is operating in a low power state. The transmitter circuit has a power consumption level below a threshold power level in the low power state.

Power consumption control for transmitters of retimers in high speed data communication

A method of forming an integrated circuit includes: forming a dielectric layer, a hard mask layer, a film layer and a photoresist layer; and patterning the photoresist layer to form a via mask, where the via mask is oversized, such that the via mask extends across opposing sides of a metal line mask in the hard mask layer. The method further includes: etching the film layer and the dielectric layer based on the patterned photoresist layer; ashing the photoresist layer and the film layer; etching the dielectric layer based on a pattern of the hard mask layer to provide a via region and a metal line region; etching the hard mask layer and the dielectric layer; and performing a plurality of dual damascene process operations to form a via in the via region and a metal line in the metal line region in the integrated circuit.

Creating an aligned via and metal line in an integrated circuit including forming an oversized via mask

Aspects of the disclosure provide an integrated circuit (IC) chip with an on-chip transformer. The on-chip transformer includes a primary inductor and a secondary inductor. The primary inductor is configured to have a first-primary coil portion formed of a first patterned metal trace disposed in a first metal layer and a second-primary coil portion formed of a second patterned metal trace disposed in a second metal layer. The secondary inductor is configured to have a first-secondary coil portion formed of a third patterned metal trace that interleaves with the first patterned metal trace in the first metal layer and a second-secondary coil portion formed of a fourth patterned metal trace that interleaves with the second patterned metal trace in the second metal layer.

On-chip inductors

A method of forming vias aligned with metal lines in an integrated circuit is provided. The method includes: forming a stacked dielectric, capped, hard mask, and first film and photoresist layers; patterning first photoresist layer to provide metal line masks; etching hard mask layer based on patterned first photoresist layer to form metal line masks; ashing first photoresist and film layers; forming second film and photoresist layers on hard mask layer; patterning second photoresist layer to form via masks across opposing sides of metal line masks; etching second film and capped layers based on patterned second photoresist layer; ashing second photoresist and film layers; etching dielectric and capped layers based on a pattern of hard mask layer to provide via and metal line regions; etching hard mask and capped layers; and performing dual damascene process operations to form vias and metal lines in via and metal line regions.

Method of creating aligned vias in ultra-high density integrated circuits

An integrated circuit includes a substrate. The substrate includes diffusion lines. The diffusion lines include impurities diffused into the substrate. A signal line layer includes first signal lines. A first metal layer includes second signal lines. The second signal lines include a first metallic material. A second metal layer includes third signal lines. The third signal lines include a second metallic material. First contacts connect the diffusion lines to (i) a first set of the second signal lines, or (ii) a first set of the third signal lines. Second contacts connect a first set of the first signal lines to a second set of the third signal lines. Each signal line in a first set of the second signal lines includes first portions and second portions. The first portions extend towards and are not connected to the second contacts. The first portions are not parallel to the second portions.

Method and apparatus for connecting signal lines of multiple layers to certain contacts while preventing connections with other contacts

A compact and versatile sense amp is presented. Among its other features this sense amp arrangement provides a way to pre-charge bit lines while doing data scanning. Another feature is that the sense amp circuit can provide a way to set three different bit line levels used in the quick pass write (QPW) technique using dynamic latch, where quick pass write is a technique where cells along a given word line selected for programming can be enabled, inhibited, or partially inhibited for programming. Also, it can provide a convenient way to measure the cell current.

Compact sense amplifier for non-volatile memory suitable for quick pass write

Compact sense amplifier for non-volatile memory

A memory array includes a first layer, a second layer, a third layer and a contact. The first layer is disposed on a substrate. The second layer includes a first conductive line. The first conductive line includes first line segments and second line segments. Each of the second line segments are connected to a respective one of the first line segments. The first line segments extend in a first direction on the first layer. The second line segments extend in a second direction on the first layer. The first direction is different than the second direction. The third layer is disposed on the second layer. The contact is disposed through the second layer and connects the third layer to the first conductive line. One of the first line segments extends towards the contact. Each of the first and second line segments are at least a predetermined distance from the contact.

Memory and interconnect design in fine pitch

A memory array including a diffusion layer, a poly layer, a metal one layer, a metal two layer, and a contact. The diffusion layer comprises diffusion lines extending in a first direction. The poly layer comprises poly lines extending in the first direction and being arranged on top of and insulated from the diffusion layer. The metal one layer comprises metal one lines extending in the first direction and being arranged on top of and insulated from the poly layer. The metal two layer comprises a metal two line extending in the first direction and being arranged on top of and insulated from the metal one layer. The contact extends through the poly layer, and connects a metal one line to a diffusion line. A poly line further extends in a second direction to bend around the contact such that a predetermined distance separates the poly lines from the contact.

Memory cells and arrays have reduced bit line resistance. An element conductor is disposed on the top of the bit line to reduce the resistance of the bit line while maintaining a shallow bit line junction so that 200 Ohm/square or lower sheet resistances are achieved with the bit line junctions typically 20 nanometers or shallower while the doping levels in the junctions are below about 5&#xd7;10atoms/cm.

Non-volatile memory cell and array

An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer. A third signal line layer includes a plurality of third signal lines arranged on top of and insulated from the second signal line layer. A contact extends through the second signal line layer and connects at least one of the plurality of third signal lines to at least one of the first signal lines. At least one of the second signal lines further extends in a second direction to bend around the contact such that a predetermined distance separates the plurality of second signal lines from the contact.

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Fremont, CA, United States of America

Min She