Skhynix Inc.

Industry-University Cooperation Foundation Hanyang University

Samsung Electronics Co., Ltd.

Min-Seok Shin

Oh-Kyong Kwon

Dong-Il Lee

Young-Chul Sohn

Min-kyu Kim

Ja-Seung Gou

Jung-Eun Song

Hoe-Sam Jeong

Chan-Seob Park

Dong-Hak Kim

An image sensing device includes a pixel suitable for outputting a pixel signal through a read-out line during a read-out section and a precharge block suitable for precharging the read-out line to a voltage level corresponding to an initial voltage level of the pixel signal during a row non-selection section adjacent to the read-out section.

Image sensing device comprising dummy pixel row and active pixel rows coupled to read-out column line, and using a high speed active pixel row read-out method that reduces settling time by precharging the column line during a dummy pixel row selection time between active pixel row selection times

A data readout apparatus may include a counter array including an address decoder and a counter circuit, the address decoder being configured to receive an address, the counter circuit being coupled to the address decoder and perform a counting operation based on a column address, a sense amplifier array coupled to the counter array to read out the data from the counter array, a clock driver arranged adjacent to the center of the counter array to distribute clock pulses, a first precharge circuit arranged at one side of the counter array and structured to receive the clock pulses from the clock driver and perform a precharge operation, and a second precharge circuit arranged at the other side of the counter array and structured to receive the clock pulses from the clock driver and perform the precharge operation.

High-speed data readout apparatus and CMOS image sensor using the same

A data readout apparatus may include a comparison circuit structured to compare a pixel signal with the ramp signal to generate a comparison result, a counter array structured to receive the comparison results to count up with each clock pulse from a first timing until a second timing to convert a counted number of clock pulses into differential data and output the differential data through differential data lines, and a sense amplifier array structured to receive the differential data to sense and amplify the differential data based on a judge clock. The sense amplifier array can include a replica delay structured to delay the judge clock and the precharge pulse signal based on a read out timing and read out the data from the counter array at the read out timing.

A differential circuit includes a differential selection block suitable for generating differential selection signals corresponding to differential input signals in response to an enable signal and a differential loading block suitable for loading differential output signals corresponding to the differential input signals on differential lines in response to the differential selection signals.

Differential circuit and image sensing device including the same

An image sensing device includes pixel groups, each pixel group including two or more neighboring pixels and grouped into a same pattern; and a timing generator controlling the pixel groups based on one or more row units, wherein readout orders of first and second pixel groups arranged in different rows among the pixel groups are controlled differently, wherein the first pixel group reads out two or more pixel signals based on two or more first transmission control signals, wherein the second pixel group reads out two or more pixel signals based on two or more second transmission control signals, wherein the timing generator generates the first transmission control signals in a first order during one or more first row readout times, wherein the timing generator generates the second transmission control signals in a second order, which is different from the first order, during one or more second row readout times.

Image sensing device

A read-out method of an image sensing device includes: firstly counting a reset signal of a pixel signal based on a first analog gain during a first period of a unit row period; storing a result of the first counting as a previous counting result; secondly counting the reset signal based on a second analog gain; thirdly counting a data signal of the pixel signal based on the second analog gain during a second period following the first period in the unit row period; storing a first counting signal corresponding to results of the second counting and the third counting; fourthly counting the data signal based on the first analog gain during a third period following the second period in the unit row period; and storing a second counting signal corresponding to the previous counting result and a result of the fourth counting.

Counting circuit including a plurality of latch circuits and image sensing device with the counting circuit

An image sensing device includes a read-out control block suitable for generating a selection address signal and one or more address clock signals based on a source address signal, and a judge clock signal having a higher frequency than a source clock signal; and a read-out block suitable for reading out a plurality of pixel signals in response to the selection address signal, the address clock signals and the judge clock signal.

Image sensing device and read-out method of the same

An image sensing device includes a plurality of pixel groups, each pixel group including two or more neighboring pixels, and a controller suitable for controlling the pixel groups on a basis of a frame unit, wherein a readout order of the pixels in each of the pixel groups is different between present and next frames.

Image sensing device and method for driving the same

A counter includes a sampling unit suitable for sampling a logic state of a least significant bit (LSB) during a counting hold section, the counting hold section is present between first and second ramp sections; and a toggling control unit suitable for, in response to a clock and a sampling signal outputted from the sampling unit, generating the LSB according to a first voltage level of a counting target signal during a second part of the first ramp section and generating the LSB according to a second voltage level of the counting target signal during a first part of the second ramp section.

Counter, analogue to digital converter including the counter and image sensing device including the analogue to digital converter

An image sensing device includes: a pixel array including a plurality of pixels arranged at each cross point of rows and columns, wherein the pixel array comprises a plurality of pixel blocks, each including N pixels, N being a natural number equal to or greater than 2, wherein the pixel blocks sequentially output a plurality of pixel signals having pixel information on the same color N times during one or more single row times; a plurality of column lines suitable for sequentially transferring the plurality of pixel signals from the pixel blocks, each column line being shared by two adjacent columns and coupled to at least one of the pixel blocks; a plurality of averaging blocks suitable for grouping the pixel signals to overlap each other, into a plurality of pixel signal groups, and averaging the pixel signal groups to output a plurality of averaged pixel signals, wherein the number of the averaging blocks is smaller than the number of the column lines; and a plurality of conversion blocks suitable for converting the averaged pixel signals into a plurality of digital signals.

A driver includes a first level shifting unit generating a second signal swinging in a second threshold range in response to a first signal swinging in a first threshold range, a second level shifting unit generating a third signal swinging in a third threshold range in response to the second signal, a first pull-up driving unit driving an output terminal with a first high-voltage in response to the second signal, a first pull-down driving unit driving the output terminal with a first low voltage in response to the third signal, a second pull-down driving unit driving the output terminal with a second low voltage higher than the first low voltage in response to the fourth signal, and a first path coupling unit coupling the second pull-down driving unit with the output terminal in response to the second signal.

Driver and image sensing device including the same

An image sensing device includes: a pixel unit including a first sub-pixel and a second sub-pixel corresponding to a single color; a row control block suitable for controlling exposure times of the first and second sub-pixels differently from one another during an exposure time section, and controlling a first sub-pixel signal and a second sub-pixel signal to be outputted from the first and second sub-pixels during a single row line unit time during a read time section; and an image process block suitable for generating three or more image data which have different exposure times based on the first and second sub-pixel signals.

An image sensing device includes a unit pixel including one or more first sub-pixels of a white color and a plurality of second sub-pixels of a color other than the white color in a matrix, a row control block suitable for controlling the first and second sub-pixels to output sequentially first and second pixel signals during one row unit time, and an image process block suitable for processing the first and second pixel signal's.

Image sensing device for improving dynamic range

An image sensing device includes: a pixel array including a plurality of pixels arranged in row and column directions; a row control portion suitable for controlling a part of a plurality of rows included in the pixel array by an unit of two or more sequential rows so that pixel signals are simultaneously outputted from the pixel array through the sequential rows; a first readout circuit portion suitable for sequentially reading out a part of the pixel signals in row sequence order; a second readout circuit portion suitable for sequentially reading out the rest of the pixel signals in row sequence order; and a storage portion suitable for storing on row by row basis the read out signals sequentially read out in row sequence order from the first and second readout circuit portions.

Image sensing device with shared pixel architecture and efficient readout circuitry

A double data rate (DDR) counter includes a first control block suitable for toggling a counter clock according to a count mode signal and a previous state value of a sampling block; a second control block suitable for determining whether to toggle a clock signal inputted to a counting block corresponding to an (LSB+1) bit or higher; a third control block suitable for determining an enable period of the counting block; the sampling block suitable for sampling a state of the clock signal and outputting an LSB value, when an input signal transits; and the counting block suitable for performing counting according to output signals of the second and third control blocks and outputting a counter output signal having the (LSB+1) bit or higher.

Growing community of inventors

Gyeonggi-do, South Korea

Min-Seok Shin