Skhynix Inc.

Postech Academy-Industry Foundation

Min Seob Lee

Yong Ju Kim

Jung Hyun Kwon

Dong Gun Kim

Jae Yoon Sim

In Hwa Jung

Kwang Hyo Jeong

A memory system includes a memory device comprising plural memory groups, and a controller configured to independently set or adjust a page close time or a page open time for a row or a page in each of the plural memory groups based on whether there is a request to be transferred into each of the plural memory groups.

Memory system and operation method thereof

An all digital phase locked loop (ADPLL) includes an integer part phase processing circuit that outputs an integer part frequency signal using a first value and a second value. The first value is obtained by counting edges of one of a plurality of output clock signals. The second value indicates current edge position information on an edge position of an external reference clock signal with respect to the plurality of output clock signals. The ADPLL further includes a fraction part phase processing circuit that selects two adjacent output clock signals of the plurality of output clock signals according to a prediction selection signal and that generates a fraction part frequency signal using the fraction part phase signal, the prediction selection signal being generated according to a fraction part phase signal indicating fraction part phase information and a signal indicating the current edge position information.

All digital phase locked loop

Growing community of inventors

Gyeonggi-do, South Korea

Min Seob Lee