Samsung Electronics Co., Ltd.

Min-sang Kim

Sung-Min Kim

Eun-jung Yun

Ji-myoung Lee

Dong-won Kim

Sung-young Lee

Sung-Young Lee

In-Hyuk Choi

Dong-Gun Park

Chang-Woo Oh

Keun-Hwi Cho

Kyoung-hwan Yeo

Hyun-Jun Bae

Ji-Hoon Kim

Dong-Won Kim

Ming Li

Yun-chong Hwang

Kyu-dong Kim

Jeong-Dong Choe

Sung-Hwan Kim

Sung-min Kim

Dong-Uk Choi

Se-Myeong Jang

Hye-Jin Cho

Jun Ho Seo

Woun-Suck Yang

Weonwi Jang

Choong-Ho Lee

Bo-un Yoon

Chul Ho Lee

Jae-Man Yoon

Jun Hyuk Seo

Byoung-ho Kwon

Yong-Hyun Kwon

Dong-won Shin

Jun Seon Seo

Weon-Wi Jang

Keun-hwl Cho

Min-young Shin

Provided are a solid state drive (SSD) card and an electronic system including the same. The electronic system includes a main board to which an input device and an output device are connected. A central processing unit (CPU) and a platform hub (PH) are provided on the main board. The PH is electrically connected to a hybrid interface socket. The hybrid interface socket includes a secure digital (SD) card interface and a non-SD card interface. When the SSD card and the electronic system including the same are used, a storage capacity may be conveniently upgraded to a higher capacity. Also, since the hybrid interface socket is provided in place of a conventional SD card socket, additional space is not required and thus space may be efficiently used.

Solid state drive card and an electronic system including the same

Solid state drive

Gate-all-around integrated circuit devices include first and second source/drain regions on an active area of an integrated circuit substrate. The first and second source/drain regions form p-n rectifying junctions with the active area. A channel region extends between the first and second source/drain regions. An insulated gate electrode surrounds the channel region.

Gate-all-around integrated circuit devices

A field effect transistor includes a buried gate pattern that is electrically isolated by being surrounded by a tunneling insulating film. The field effect transistor also includes a channel region that is floated by source and drain regions, a gate insulating film, and the tunneling insulating film. The buried gate pattern and the tunneling insulating film extend into the source and drain regions. Thus, the field effect transistor efficiently stores charge carriers in the buried gate pattern and the floating channel region.

Field effect transistor with buried gate pattern

A semiconductor device that may control a formation of a channel is disclosed. The semiconductor device includes a gate region including a first area, an insulating layer disposed on portions of a top surface of the gate region corresponding to both ends portions of the first area, first and second electrodes formed on the insulating layer to be spaced apart from each other, an elastic conductive layer disposed between the first and second electrodes and the insulating layer and having a shape that varies according to an electrostatic force based on voltages applied to the first electrode, the second electrode, and the gate region, and a gate insulating region disposed between the elastic conductive layer and the first area of the gate region.

Semiconductor devices including a transistor with elastic channel

A method of manufacturing a semiconductor device is provided. A pattern layer is formed on a substrate defined to include a main pattern region and a dummy pattern region. A preliminary main pattern and a preliminary dummy pattern may be formed by patterning the pattern layer so that an upper surface area of the preliminary dummy pattern facing away from a surface of the substrate is less than an entire area of the dummy pattern region that is be subjected to subsequent planarization. The preliminary main pattern and the preliminary dummy pattern are partially etched to form a main pattern and a dummy pattern.

Methods of manufacturing semiconductors using dummy patterns

A memory device includes a memory cell that includes a storage node, a first electrode, and a second electrode, the storage node stores an electrical charge, and the first electrode moves to connect to the storage node when the second electrode is energized.

Switch and method of forming the same

A memory device includes a storage node, a first electrode, and a second electrode formed in a memory cell, the storage node stores electrical charges, the first electrode comprising a first portion electrically connected to a second portion, the first portion moves to connect to the storage node when the second electrode is energized.

Electromechanical switch and method of forming the same

A multibit electro-mechanical memory device comprises a substrate, a bit line on the substrate, a first interlayer insulating film on the bit line, first and second lower word lines on the first interlayer insulating film, the first and second lower word lines separated horizontally from each other by a trench, a spacer abutting a sidewall of each of the first and second lower word lines, a pad electrode inside a contact hole, first and second cantilever electrodes suspended over first and second lower voids that correspond to upper parts of the first and second lower word lines provided in both sides on the pad electrode, the first and second cantilever electrodes being separated from each other by the trench, and being curved in a third direction that is perpendicular to the first and second direction; a second interlayer insulating film on the pad electrode, first and second trap sites supported by the second interlayer insulating film to have first and second upper voids on the first and second cantilever electrodes, and first and second upper word lines on the first and second trap sites.

Method of manufacturing multibit electro-mechanical memory device having movable electrode

In semiconductor devices, and methods of formation thereof, both planar-type memory devices and vertically oriented thin body devices are formed on a common semiconductor layer. In a memory device, for example, it is desirable to have planar-type transistors in a peripheral region of the device, and vertically oriented thin body transistor devices in a cell region of the device. In this manner, the advantageous characteristics of each type of device can be applied to appropriate functions of the memory device.

Field effect transistors with vertically oriented gate electrodes and methods for fabricating the same

In a method of manufacturing a semiconductor device, an active channel pattern is formed on a substrate. The active channel pattern includes preliminary gate patterns and single crystalline silicon patterns that are alternately stacked with each other. A source/drain layer is formed on a sidewall of the active channel pattern. Mask pattern structures including a gate trench are formed on the active channel pattern and the source/drain layer. The patterns are selectively etched to form tunnels. The gate trench is then filled with a gate electrode. The gate electrode surrounds the active channel pattern. The gate electrode is protruded from the active channel pattern. The mask pattern structures are then removed. Impurities are implanted into the source/drain regions to form source/drain regions. A silicidation process is carried out on the source/drain regions to form a metal silicide layer, thereby completing a semiconductor device having a MOS transistor.

Semiconductor device having a multi-channel type MOS transistor

Growing community of inventors

Seoul, South Korea

Min-sang Kim