Sandisk Technologies Inc.

Western Digital Technologies, Inc.

Min Peng

YenLung Li

Hua-Ling Cynthia Hsu

Chen Chen

Daniel Edward Tuers

Grishma Shah

Sahil Sharma

Cynthia Hsu

Yen-Lung Li

Zhuojie Li

Mitsuyuki Watanabe

A data storage device including, in one implementation, a NAND memory and a controller. The NAND memory includes a read/write circuit configured to determine and store initial physical column addresses for each plane included in the NAND memory. The controller is configured to send a read-transfer command and a one-byte address to the NAND memory. The read/write circuit is also configured to retrieve a first initial physical column address from the initial physical column addresses stored in the NAND memory after the NAND memory receives the one-byte address from the controller. The first initial physical column address is associated with a die address and a plane address included in the one-byte address. The read/write circuit is further configured to retrieve a first set of data stored at the first initial physical column address. The read/write circuit is also configured to output the first set of data to the controller.

Overhead reduction in data transfer protocol for NAND memory

In a non-volatile memory circuit, performance is improved by converting data between a serial format, for transfer on and off of the memory circuit, and a parallel format, for transfer to and from the memory latches used for read and writing data into the memory array of the memory circuit. The memory array is split into M+N divisions, but transferred with a degree of parallelism of M, allowing M words of data to be transferred in parallel at a fixed transfer rate while allowing for up to N bad columns in a transfer. In the write path, a column skipping mechanism is used when converting words of write data into a parallel format. In the read path, a set of (M+N) to 1 multiplexers is used to align the word of read data so that read data can be transferred at a fixed rate and without any added latency.

Centralized fixed rate serializer and deserializer for bad column management in non-volatile memory

Aspects of a storage device are provided that reduce calculations for identifying physical locations of data during a read operation. In one aspect, a memory device includes one or more memory arrays. Each array includes multiple chunks of memory. The device includes a first set of registers for storing prefixed starting addresses for each array. The device further includes control logic that may identify bad physical address in each array. For each successive chunk in each array and based on the prefixed starting address and the bad physical address locations, the device may determine a pointer to a starting physical address for the chunk. The pointer may be stored in a second set of registers for use in register read operations.

Circuit to reduce gating overall system performance

Apparatuses and techniques are described for transferring data out of a memory device with low latency. Data can be stored in data transfer latches for NAND strings arranged in columns in divisions of a block. Data can be output from the data transfer latches for different columns in different divisions in each transfer. For example, the data output can include data from an nth column in some divisions and an n+1column in other divisions. This avoids outputting unwanted data at the start of a data transfer. The data from the data transfer latches is output to a data pipeline and then to a set of control latch circuits. The data can be clocked out from a last control latch circuit of the set in a desired division order by use of separate multiplexer control signals for the control latch circuits.

Low latency data transfer

Apparatuses and techniques are described for accessing redundant columns of data in a memory device. To facilitate scaling of a memory device and reduce a clock rate used to access latches of the redundant columns in program and read operations, one or more first-in, first out (FIFO) buffers are provided to output data to, and receive data from, the latches. The FIFO buffers act as an interface between a controller and the latches, and exchange data with the controller at a relatively high clock rate, and exchange data with the latches of the redundant columns at a slower clock rate. During a read operation, the FIFO can prefetch read data from one or more columns and store it until it is needed to replace the data of a defective primary column.

Asynchronous FIFO buffer for redundant columns in memory device

In non-volatile memory circuit, the area devoted to the cache buffer of the read and write circuitry is reduced through the sharing of data latches. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, each of the columns has an associated set of data latches, including one or more data latches for each bit line of the column. Data is transferred in and out of the read and write circuit on a data bus, where data is transferred between the data latches and the data bus through a set of transfers latches. The area used by the latch structure is reduced by sharing the transfer latches of the read and write circuitry between the data latches of multiple columns.

Non-volatile memory with reduced data cache buffer

In a non-volatile memory circuit, read and write performance is improved by increasing the transfer rate of data through the cache buffer during read and write operations. In an array structure where memory cells are connected along bit lines, and the bit lines organized into columns, pairs of data words are stored interleaved on the bit lines of a pair of columns. Data is transferred in and out of the read and write circuit on an internal bus structure, where part of the transfer of one word stored on a pair of columns can overlap with part of the transfer of another word, accelerating transfer times for both read and write.

Non-volatile memory with fast data cache transfer scheme

Apparatuses, systems, and methods are disclosed for skip inconsistency correction. A skip circuit is configured to skip memory units for read operations and write operations of a memory array, based on a record of memory units identified as faulty. A skip inconsistency detection circuit is configured to detect a skip inconsistency in read data from a memory array. A correction circuit is configured to correct a skip inconsistency and output corrected read data.

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San Jose, CA, United States of America

Min Peng