Synopsys, Inc.

Min Pan

Tao Lin

Tao Huang

Zuo Dai

Jaehan Jeon

Aiqun Cao

Anand Kumar Rajaram

Xiaojun Ma

Cheng-Liang Ding

Partha Das

Tobias Bjerregaard

Feng Sheng

Konstantinos Tsirogiannis

A system and method updates a clock tree based on skew values of the circuit design. The clock tree is updated by obtaining a circuit design that includes circuit elements and a clock tree. The clock tree includes clock sources and clock sinks. Data path slack values for the clock tree are determined based on the clock sources and the clock sinks. Further, clock arrival values for the clock tree are determined based on the clock sources and the clock sinks. A first total local skew value of the circuit design is determined based on the data path slack values, and the clock arrival values, and updating the clock tree based on the first total local skew value.

Circuit design having an improved clock tree

A system and method for changing a circuit design are described. The method includes generating a propagation graph for the circuit design and estimating slack values for some of the paths in the propagation graph. The method also includes making a virtual change to the circuit design and determining whether to accept or reject the change based on how the change affects the estimated slack values.

System for making circuit design changes

A method of determining a clock tree for a circuit includes, in part, generating a multitude of symmetric clock configurations characterized by a multitude of columns and a multitude of rows. For each symmetric clock configuration, the method further includes, in part, selecting positions of a multitude of tap points defined by a multitude of end points of the multitude of rows, estimating a first cost from a tree root to each of the first multitude of tap points, estimating a second cost from the multitude of tap points to a multitude of clock sinks associated with the multitude of tap points, and determining the symmetric clock configuration cost in accordance with the first cost and the second cost.

Automatic global clock tree synthesis

An implementation-quality synthesis process begins with a logical design of an integrated circuit and, through a series of steps, generates a fully synthesized physical design of the integrated circuit. One of the steps is clock synthesis, which generates the clock network for the integrated circuit. In certain embodiments, a method includes the following steps. A reduced clock synthesis process is applied, rather than the implementation-quality clock synthesis process. This generates a clock network for the logical design, which will be referred to as a proxy clock network because it is used as a proxy to estimate power consumption of the fully synthesized clock network. Because the reduced clock synthesis process runs much faster than the implementation-quality clock synthesis process, the front end designer may use these power estimates in the front end design process, including to explore different design variations in the logical design.

Clock network power estimation for logical designs

Dual-structure clock tree synthesis (CTS) is described. Some embodiments can construct a set of upper-level clock trees, wherein each leaf of each upper-level clock tree is a root of a lower-level clock tree. Each upper-level clock tree can be optimized to reduce an impact of on-chip-variation and/or cross-corner variation on clock skew. Next, for each leaf of each upper-level clock tree, the embodiments can construct a lower-level clock tree to distribute a clock signal from the leaf of the upper-level clock tree to a set of clock sinks. The lower-level clock tree can be optimized to reduce latency, power consumption, and/or area.

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Fremont, CA, United States of America

Min Pan