At&t Bell Laboratories

Lucent Technologies Inc.

American Telephone & Telegraph Co., At&t Bell Laboratories

Min-Liang Chen

Chung W Leung

Pradip Kumar Roy

Sailesh Chittipeddi

Kurt George Steiner

Taeho Kook

Chih-Yuan Lu

Cheryl Anne Bollinger

William T Cochran

David P Favreau

Daniel J Vitkavage

Nun-Sian Tsai

Daniel Mark Wroge

Richard A Powell

The base layer of high quality spacers, such as those used on the sidewalls of the gate stack of submicron devices (e.g., MOSFETs, EPROMs), are formed as composite, multi-layered structures of silicon oxides or of silicon oxides and silicon nitride.

Method of fabricating semiconductor devices and integrated circuits

A thin film transistor is formed by depositing amorphous silicon and forming a gate structure and then using a high-pressure oxidation to form a high-quality gate oxide that has a layered structure.

Method of making thin film transistors including recrystallization and

A method of making a silicided inverse T-gate with an L-shaped silicon spacer and nitride sidewall spacers is described. The L-shaped spacer is electrically connected to the gate.

Transistor with inverse silicide T-gate structure

Self-aligned contacts are formed to regions between closely spaced features by a method which uses differential etch rates between first and second dielectrics deposited over the closely spaced features.

Integrated circuit with planar dielectric layer

In the manufacture of semiconductor integrated-circuit devices, electrical contact to semiconductor regions such as, e.g., source and drain regions of field-effect transistors typically is made by a structure in which a silicide is intermediary to silicon and metal. The invention provides for processing, after window formation and before metal deposition, which includes deposition of a silicide-forming material, and annealing in a non-oxidizing atmosphere. Preferably, the atmosphere includes a component which forms a conductive compound with the silicide-forming material. Resulting contact structures have good step coverage, low contact resistance, low interdiffusion of metal into semiconductor, and fail-safe operation in the event of breaks due to electromigration. Moreover, in the case of misalignment of a window, a contact region may be extended laterally by dopant diffusion, thereby safeguarding the junction. Tolerance to window misalignment permits increased packing density, e.g., in dynamic random-access memory arrays.

Contact metallization of semiconductor integrated-circuit devices

A p-type tub in a CMOS integrated circuit is isolated from the adjacent n-type tub by means of a field oxide having a p-type channel stop region formed by a boron ion implant. The depth of the ion implant is selected so that the peak of the boron concentration is located immediately under the field oxide region that is subsequently grown. In addition, the implant is allowed to penetrate into the active device regions, producing a retrograde boron concentration in the n-channel region. This technique simultaneously improves device isolation and n-channel transistor punch-through characteristics, allowing the extension of CMOS technology to sub-micron device geometries.

CMOS integrated circuit having improved isolation

Contacts to the gate electrode of a first field-effect transistor and the source/drain region of a second field-effect transistor are formed using a silicide as a local interconnect.

Method of making electrical contacts to gate structures in integrated

When making CMOS logic circuits, for example an inverter, it is frequently necessary to connect the sources of the p and n channel transistors to their respective tubs (n and p, respectively). The prior art required either a large contact window covering both source and tub regions, or else two standard size contact windows. The present technique forms the tub tie connection by the use of the same silicide layer that is formed on the source/drain regions, which typically also forms a gate silicide in the self-aligned silicide (i.e., 'salicide') process. A conventional window may then be used to connect the silicide tub tie (and hence the source/tub regions) to a power supply conductor. A space saving is obtained, and increased freedom for placing the power supply contact window is obtained.

Integrated circuit with improved tub tie

Silicides are important for submicron VLSIC technology. Problems have been found in forming silicides by known techniques involving simply depositing a metal film and heating that metal to form a silicide layer. This invention solves the problems through recognition that polymeric contamination can be left on the surface from commonly-used previous reactive ion etch steps, and removes any such contamination to metal deposition by the additional step of heating in dry oxygen at a low temperature, such as 800 degrees Centigrade, before the contamination has been significantly hardened.

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Allentown, PA, United States of America

Min-Liang Chen