Mosel Vitelic Corporation

Lucent Technologies Inc.

Promos Technologies, Inc

Min-Liang Chen

Chih-Hsien Wang

Nan-Hsiung Tsai

Thomas Chang

Ying-Kit Tsui

Jau-Nan Kau

Chih-hsun Chu

San-Jung Chang

Saysamone Pittikoun

Wei-Jing Wen

G S Shiao

Hai-Jun Zhao

Werner Juengling

Rebecca Yicksin Tang

A method of stacking wafers includes: providing a first wafer including a first metal connection layer; forming a first passivation layer over the first metal connection layer; forming a first bondpad in the first passivation layer to form a first bondpad layer; providing a second wafer including second metal connection layer; forming a second passivation layer over the second metal connection layer; forming a second bondpad in the second passivation layer to form a second bondpad layer; forming at least one of a first conductive adhesive layer over the first bondpad layer and a second conductive adhesive layer over the second bondpad layer; and stacking the second wafer on the first wafer by bonding respective faces of the second bondpad layer with the first bondpad layer via the at least one of the first conductive adhesive layer and the second conductive adhesive layer.

Stacked semiconductor device and method

A dynamic random access memory (DRAM) integrated circuit (,). The DRAM (,) includes a recessed region (,) defined in a semiconductor substrate (,). This recessed region has substantially vertical sides (,) extending from a bottom surface (,). A field effect transistor (,) is defined adjacent to the recessed region (,). A capacitor structure, including a lower capacitor plate (,), a capacitor dielectric (,), and an upper capacitor plate (,), is defined in the recessed region (,) and over the field effect transistor (,), thereby providing a greater capacitor surface.

High density memory structure

A process for completely removing TiN residue existing outside contact windows is described: electrical elements are formed on a silicon substrate, an insulating layer is then formed over the entire silicon substrate, next, the insulating layer is partially etched to form metal contact windows, a TiN barrier layer and a tungsten metal layer are then sequentially deposited overlaying the insulating layer and filling into the metal contact windows, two stage CMP process is performed to remove the metal and TiN barrier layers exposed outside the contact windows respectively, finally, an dry etching step employing HCl/Cl.sub.2 plasmas is performed to make sure there is not any TiN residues left outside contact windows.

Completely removal of TiN residue on dual damascence process

A method of forming an integrated circuit device, and in particular a CMOS integrated circuit device, having an improved lightly doped drain region. The methods include the steps of providing a semiconductor substrate with a P type well region and an N type well region. Gate electrodes are formed overlying gate dielectric over each P type well and N type well regions. The present LDD fabrication methods then provide a relatively consistent and easy method to fabricate CMOS LDD regions with N type and P type implants at a combination of different dosages and angles using first and second sidewall spacers, with less masking steps and improved device performance.

Method for forming LDD CMOS using double spacers and large-tilt-angle

A method of making a resistor begins with forming a field effect transistor on a silicon semiconductor substrate. Then a first insulating layer is deposited on the field effect transistor. The first insulating layer is etched by the photolithography and etching techniques to form a bit line contact, and a bit line is subsequently formed. Next, upon the entire structure, a second insulating layer is formed and etched by the photolithography and ion etching techniques to form a contact hole with high aspect ratio. A polysilicon layer is deposited across the contact hole and the polysilicon outside the contact hole is removed, forming a polysilicon plug in the contact hole. Then, a third insulating layer is formed and etched to form a contact hole for metallurgy. After a first metal interconnection is formed, a third insulating layer is formed upon the entire structure and then etched to form a via hole by the photolithography and plasma etching techniques. A second metal interconnection is then formed and completes the static random access memory (SRAM) cell.

Method of making a resistor utilizing a polysilicon plug formed with a

A method for fabricating a CMOS integrated circuit device with less masking steps than a conventional device. The present method includes a step of providing a semiconductor substrate with a well region, a gate dielectric layer, and a polysilicon gate electrode. The gate dielectric layer is overlying the well region, and the polysilicon gate electrode is overlying the gate dielectric layer. The present method also includes forming a first thermal oxide thickness overlying the polysilicon gate electrode layer and a second thermal oxide thickness overlying exposed regions. The first thermal oxide thickness is greater than the second thermal oxide thickness, and both layers are defined during the same step. A mask exposes first LDD regions and first source drain regions. The present method then angle implants a first impurity through the first thermal oxide thickness and the second thermal oxide thickness, and implants a second impurity through the second thermal oxide thickness, thereby forming the completed source/drain region in a single masking step.

Method for forming LDD CMOS

The invention provides an isolation technique using fewer process steps and a double charged implantation step (141) for defining a well region (139) of a CMOS integrated circuit device. The invention provides steps of providing a semiconductor substrate comprising an multiple layer of films (105, 107, 109). These films include an oxide layer (105) overlying the substrate, a polysilicon layer (107) overlying the oxide layer, and a nitride layer (109) overlying the polysilicon layer. The invention also uses a step of removing a first portion of the nitride layer and a first portion of the polysilicon layer defined underlying the first portion of the nitride layer and removing a second portion of the nitride layer and a second portion of the polysilicon layer defined underlying the second portion of the nitride layer. This sequence of steps provides a partially completed semiconductor structure that defines isolation regions before forming well regions for active devices.

Method for manufacturing semiconductor devices using double-charged

The present invention is related to a method of fabricating borderless metal to contact structure. A dielectric layer is deposited on the silicon semiconductor wafer. The first photoresist pattern is formed by the conventional lithography technique. Then, the dielectric layer is partially etched to formed the first trench and second trench. The first trench is used as a contact hole, while the second trench is for second metal interconnection line. Thereafter, the second photoresist pattern which is only exposing the first trench region is formed. By using the second photoresist pattern as an etching mask, the dielectric layer is etched through to form the contact which is the place for the first metal line and second metal line to be electrically contacted. After the first and second photoresist patterns are stripped, the second metal layer is deposited to fill into the contact and the second trench as second metal interconnection lines. Finally, the second metal layer and a portion of the second dielectric layer are polished by chemical mechanical polishing (CMP) technique to planarize the wafer surface. A borderless metal to contact structure according to the present invention is achieved.

Method of forming borderless metal to contact structure

The present invention discloses a double poly metal oxide/nitride/oxide semiconductor electrically erasable programmable read only memory (EEPROM) for use in semiconductor memories. The EEPROM structure includes a select gate, an oxide.backslash.nitride.backslash.oxide layer, and a control gate. The control gate is formed on the oxide.backslash.nitride.backslash.oxide layer. A lightly doped drain (LDD) structure is formed adjacent to the drain and underneath the control gate.

Method of making double-poly MONOS flash EEPROM cell

The present invention is related to a process for fabricating a MOS device having a short channel. The process according to the present invention includes the steps of (a) providing a semiconductor substrate and forming a gate structure on the semiconductor substrate; (b) implanting impurities of a first charge type to the semiconductor substrate with the gate structure serving as a mask to form a first source/drain region having a predetermined impurity concentration; (c) pocket-implanting impurities of a second charge type to the resulting semiconductor substrate with the gate structure serving as a mask to form a second source/drain region having a predetermined impurity concentration; and (d) forming a gate side wall on a flank of the gate structure, and implanting impurities of the first charge type to the resulting semiconductor substrate with the gate structure and the gate side wall serving as a mask to form a third source/drain region having a predetermined impurity concentration. The present invention is characterized in that no threshold voltage adjustment implantation to the semiconductor substrate is needed prior to the growth of the gate structure, and in stead, the diffusion ability of the pocket-implanted impurities in the step (c) can concurrently adjust the threshold voltage of the device.

Process for fabricating MOS device having short channel

A method of fabricating the self-registered cylindrical capacitor of high density Dynamic Random Access Memory (DRAM) cells. A first polysilicon layer which is the storage node of the capacitor is deposited overlaying the entire silicon substrate surface. A dielectric layer is formed overlaying the first polysilicon layer. Then, the dielectric layer and the first polysilicon layer are polished by CMP to form the cylindrical shape capacitor storage nodes. The self-registered cylindrical polysilicon storage nodes are formed by CMP technique without using the extra mask as the conventional method would. The first polysilicon storage nodes are treated by hot phosphoric acid (H.sub.3 PO.sub.4) to form the rugged surface that can tremendously increase the surface area of the capacitor. Therefore, the cylindrical capacitor storage node of the DRAM capacitor of this method has much greater surface area so as to increase the capacitance value of the DRAM capacitor, that can achieve high packing density of the integrated circuit devices.

Self-registered cylindrical capacitor of high density DRAMs

A method and structure for a lower capacitor electrode for a dynamic random access integrated circuit. A polysilicon gate layer is formed over a thin layer of oxide in a first region of a semiconductor substrate. Another oxide layer is then formed overlying the polysilicon gate layer. A polysilicon layer which was doped by S/D implant including the lower capacitor electrode self-aligns and forms overlying a second region of the semiconductor substrate and over the oxide layer on the polysilicon gate layer. A nitride layer forms on the lower capacitor electrode portion overlying the second region. Exposed portions of the polysilicon layer are then oxidized. The S/D was formed by driving dopant from implanted second layer polysilicon. Portions of polysilicon under the nitride layer corresponding to the lower capacitor electrode oxidizes at a slower rate than the exposed portions of the polysilicon. Such sequence of steps forms a self-aligned lower capacitor electrode for a dynamic random access memory integrated circuit.

Semiconductor having self-aligned polysilicon electrode layer

A dynamic random access memory (DRAM) integrated circuit (10). The DRAM (10) includes a recessed region (20) defined in a semiconductor substrate (22). This recessed region has substantially vertical sides (34) extending from a bottom surface (32). A field effect transistor (18) is defined adjacent to the recessed region (20). A capacitor structure, including a lower capacitor plate (26), a capacitor dielectric (28), and an upper capacitor plate (30), is defined in the recessed region (20) and over the field effect transistor (18), thereby providing a greater capacitor surface.

Method of forming a bit-line and a capacitor structure in an integrated

A novel electrically erasable programmable read only memory (EEPROM) cell for use in semiconductor memories includes a polyspacer floating gate. The EEPROM structure also includes a select gate covering a part of the channel of the EEPROM cell, with a polysilicon spacer adjacent to the select gate. The polysilicon spacer implements a floating gate that holds charge to program the EEPROM cell. In one embodiment, a isolation layer separates the select gate and the floating gate. The isolation layer and the floating gate extends over the remaining part of the channel. A second isolation layer is formed over select gate and the floating gate. A control gate is formed on the isolation layer. Between the drain and the control gate is the second isolation layer. A lightly doped drain (LDD) structure is formed at the drain adjacent.

Growing community of inventors

Hsinchu, Taiwan

Min-Liang Chen