Samsung Electronics Co., Ltd.

Claroptic Co., Ltd.

Min-kyu Song

Geun-Soon Kang

Seong-won Kim

Eu-Ro Joe

Gea-ok Cho

You-sam Na

An integrated optical engine based on an embodiment of the invention includes: a projecting system for projecting light to the exterior; an imaging system for receiving light from the exterior; a camera body, to which the projecting system and the imaging system are coupled; and a base coupled to the rear of the camera body. A first insertion recess extends along the lengthwise direction of the camera body and has the same diameter as the outer diameter of the projecting system such that the projecting system is movable within the first insertion recess along only the lengthwise direction, and a second insertion recess extends along the lengthwise direction of the camera body and has the same diameter as the outer diameter of the imaging system such that the imaging system is movable within the second insertion recess along only the lengthwise direction.

Integrated optical engine having camera

A high-speed and low-power encoder and an encoding method, wherein the encoder includes a switching unit for receiving a thermal code of a predetermined number of bits received in series, and outputting one bit among the received bits as a most significant bit and the other bits in parallel, and an encoder for dividing the bits received from the switching unit in parallel into groups having a predetermined number of bits, encoding the bits in each group into a predetermined number of bits, selecting one group of encoded bits using bits not used by the groups, and outputting least significant bits together with the most significant bit output from the switching unit.

High speed encoder and method thereof

Energy economized pass-transistor logic circuit and full adder using the

Disclosed is an integrated pass-transistor logic circuit which includes a conditional sum adder. This sum adder has seven sum generation blocks of module form and two carry generation blocks. With the sum adder, before carry propagation which is generated through multiplexer chain in respective sum generation blocks arrives at the final stage of the multiplexer chain, the final stage is driven by block carry signals BC.sub.i and /BC.sub.i provided from the respective carry generation blocks. The carry generation and the sum generation occur individually in the conditional sum adder. The sum generation blocks are constituted with pass-transistor logic and the carry generation blocks with Complementary Metal Oxide Semiconductor (CMOS) logic, the sum adder has a more faster operation speed and a more lower power dissipation, as compared with the prior art conditional sum adder having either the pass-transistor logic or the CMOS logic.

Conditional sum adder using pass-transistor logic and integrated circuit

A CMOS output buffer circuit includes a predriving circuit which generates two predriving signals, a main driving circuit which has a plurality of parallel connected pull-up transistors and a plurality of parallel connected pull-down transistors, and a sequential driving circuit which provides sequential pull-up and pull-down driving signals to the pull-up and pull-down transistors, respectively. The main driving circuit generates the output signal according to the sequential pull-up or pull-down driving signals, whereby the output signal is developed step by step into either the power supply potential or the ground potential. In the manner, any spike in the switching current is considerably mitigated, thereby reducing switching noise.

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Seoul, South Korea

Min-kyu Song