Skhynix Inc.

Hynix Semiconductor Inc.

Other

Hyundai Electronics Ind. Co., Ltd.

Min Kyu Lee

Chi Wook An

Nack Hyun Kim

Seok Jin Joo

Hyung Seok Kim

Kyung Pil Hwang

Ju In Kim

Keum Hwan Noh

Sook Kyung Kim

Dong Wook Kim

Hee Hyun Chang

Nam Hoon Kim

Dong Jae Jung

In Geun Lim

Shin Hye Lee

Kyoung Hoon Lim

Hee Youl Lee

Jung Ryul Ahn

Jum Soo Kim

Jun Hyuk Lee

Dong Kee Lee

Deung Kak Yoo

Sung Won Bae

Sun Kyu Park

The present technology includes a memory device, a memory system including the memory device, and a test operation of the memory device. The memory device includes a memory block connected to word lines and select lines, a bit line connected to the memory block, a voltage generator configured to generate a test voltage to be applied to a selected line among the word lines and the select lines, a page buffer configured to sense a voltage of the bit line to store and output test data, and a control logic circuit configured to determine whether a first defect exists in the memory block according to the test data.

Memory device, memory system including the memory device, and test operation of the memory device

A data storage device includes a nonvolatile memory device including dies including word line groups in which word lines are grouped; and a controller. The controller includes a word line health rating logic configured to determine a health rating of each word line and a health rating of each word line group based on state information on each of health rating factors associated with the word lines; a memory including a word line health rating table in which the health rating of each word line and the health rating of each word line group are stored; and a mapping logic configured to generate a management target logical super block by mapping one word line group having a lowest health rating and word line groups having a highest health rating, and generate a normal logical super block by mapping word line groups having intermediate health ratings.

Data storage device and operating method thereof

An error correction code (ECC) unit includes an error correction code (ECC) encoder configured to perform error correction code (ECC) encoding for each of a first data group and a second data group sharing at least one data with the first data group; and an error correction code (ECC) decoder configured to perform error correction code (ECC) decoding for each of the first data group and the second data group. The ECC decoder performs the ECC decoding for the second data group when the ECC decoding for the first data group fails, and does not perform the ECC decoding for the second data group when the ECC decoding for the first data group succeeds.

Error correction code unit and error correction method

A method for operating a semiconductor memory device may include applying a program pulse for programming data of a first page included in the semiconductor memory device. The method may include determining whether the number of times of applying the program pulse has exceeded a first critical value. The method may include performing an error bit check on a second page coupled to the same word line as the first page, based on the determined result of whether the first critical value has been exceeded.

Memory system and method for operating semiconductor memory device

The semiconductor memory device may include a memory cell array and a peripheral circuit. The memory cell array may include a plurality of memory blocks. The peripheral circuit may perform a multi-page read operation on a selected memory block among the plurality of memory blocks. The peripheral circuit may select a first word line and a second word line, which are coupled to the selected memory block, and perform the multi-page read operation on the first and second word lines.

Semiconductor memory device and method related to operating the semiconductor memory device

An error correction code processing method includes performing a first encoding operation for a data group of a first direction; performing a second encoding operation for a data group of a second direction, wherein the data group of the first direction shares one or more data with the data group of the second direction; performing a first decoding operation of correcting an error included in the data group of the first direction; and performing a second decoding operation of correcting an error included in the data group of the second direction when the first decoding operation fails.

Error correction method of data storage device

Disclosed is a semiconductor memory device. The semiconductor memory device includes: a first memory block; and a second memory block sharing a block word line with the first memory block, in which the block word line includes a first block word line disposed so as to overlap the first memory block and a second block word line disposed so as to overlap the second memory block. According to the present disclosure, it is less likely to have an operation failure.

Semiconductor memory device

Disclosed are a semiconductor memory device, and an operating method thereof. The semiconductor memory device includes: a memory cell array including a plurality of memory cells; a peripheral circuit configured to perform a program pulse application operation and a verification operation on the memory cell array; a pass/fail check circuit configured to output a pass/fail signal according to a result of the verification operation; and a control logic configured to control the peripheral circuit to perform the program pulse application operation and the verification operation such that two or more program pulses are continuously applied during the program pulse application operation, and first and second verification operations are continuously performed during the verification operation.

Semiconductor memory device and operating method thereof

An embodiment of the invention may provide a semiconductor memory device including a memory cell array including a plurality of memory cells, a peripheral circuit unit configured to perform a program operation with respect to a memory cell selected from the plurality of memory cells, wherein first to third program voltage applying operations and first to third verifying operations are alternatively performed, and a control logic configured to control the peripheral circuit unit to perform the first to third program voltage applying operations and the first to third verifying operations and to increase a second program voltage applied during the second program voltage applying operation more than a first program voltage applied during the first program applying operation by a first step voltage and a third program voltage applied during the third program voltage applying operation more than the second program voltage by a second step voltage.

Semiconductor memory device, memory system having the same and operating method thereof

A semiconductor memory device according to an embodiment of the present invention includes a first cell string and a second cell string coupled to a first word line group and a second word line group, respectively. An operating method of the semiconductor memory device may include forming a channel in the second cell string by applying a pass voltage to the second word line group, reflecting data of a selected memory cell coupled to a selected word line of the first word line group, among memory cells of the first cell string, on the channel of the second cell string through the bit line, and determining the data of the selected memory cell by sensing a quantity of electric charge of the second cell string through the bit line.

Semiconductor memory apparatus and method for reading data from the same

A semiconductor memory device, a memory system including the same and an operating method thereof are set forth. The semiconductor memory device includes a memory cell array having a plurality of memory cells, peripheral circuits configured to perform a program operation using an incremental step pulse programming (ISPP) method on selected memory cells from among the plurality of memory cells. The semiconductor memory device includes an additional program using set program voltages to set memory cells, and a control logic configured to control the peripheral circuits to perform the program in the manner of the ISPP method and the additional program.

Semiconductor memory device, memory system including the same and operating method thereof

A semiconductor device includes a memory block including even memory cells configured to form an even page and odd memory cells configured to form an odd page. The semiconductor device may also include an operation circuit configured to perform a program operation on the even memory cells and the odd memory cells. A first verify operation may separately verify the even memory cells and the odd memory cells, and a second verify operation may simultaneously verify the even memory cells and the odd memory cells. Further, the operation circuit may be configured to selectively perform the first verify operation and the second verify operation depending on a number of adjacent program fail cells in response to a verify result value.

Semiconductor device and program fail cells

A semiconductor device includes a memory block including memory cells coupled to word lines, and an operation circuit suitable for performing a program operation and a verify operation on memory cells coupled to a selected word line, wherein, when performing the program operation, the operation circuit applies a first program allowance voltage to a bit line of a first program fail cell to keep a program fall status, and a second program allowance voltage having a voltage level different from the first program allowance voltage to a bit line of a second program fail cell to change a program pass status to a program fail status.

Growing community of inventors

Icheon-si, South Korea

Min Kyu Lee