Samsung Electro-mechanics Co., Ltd.

Min Jung Cho

Byung Kun Kim

Yu Hong Oh

Yun Sung Kang

Yun Hee Kim

Chang Hak Choi

Myung Sam Kang

Mi Sun Hwang

Kyung Ryul Lee

Ok Tae Kim

Jun Oh Kim

Suji Kang

Seon Ha Kang

Su Ji Kang

Kil Yong Yun

Su Yeon Lee

Yuhong Oh

Gil Yong Shin

Won Mi Choi

A multilayer capacitor includes a body including a stack structure in which a plurality of dielectric layers are stacked and a plurality of internal electrodes stacked with respective dielectric layers interposed therebetween, external electrodes disposed on external surfaces of the body and connected to the internal electrodes, and an insulating layer covering a surface of the body. One of the external electrodes includes a metal layer connected to the insulating layer, and the insulating layer includes an oxide of a metal component of the metal layer.

Multilayer capacitor and method of manufacturing the same

A multilayer electronic component includes a body including dielectric layers and internal electrodes alternately disposed with the dielectric layers and external electrodes disposed on the body and connected to the internal electrodes. The one of the internal electrodes includes Ni, Ba, Ti, O, and Tb, and a content of Tb relative to a sum of contents of Ni, Ba, Ti, O, and Tb is 0.45 to 3.0 wt %.

Multilayer electronic component

A multilayer electric component includes a body including a dielectric layer and internal electrodes alternately stacked with the dielectric layer interposed therebetween and external electrodes disposed on the body and connected to the internal electrodes, wherein the internal electrodes include Cu and Ni and a coefficient of variation (CV) value of Cu/Ni (percent by weight) in a region thereof, 5 nm deep from an interface with the dielectric layer is 25.0% or less.

A multilayer electronic component includes a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer interposed therebetween in a first direction; and an external electrode disposed on the body and connected to the internal electrode, wherein 0.46 to 1.08 at % is a range of an indium (In) content compared to nickel (Ni) and indium (In) contents in a surface layer portion of the internal electrode.

Multilayered electronic component

Multilayer capacitor

A multilayer electronic component includes a body including a dielectric layer and internal electrodes alternately stacked with the dielectric layer interposed therebetween; and an external electrode disposed on the body and connected to the internal electrodes. One of the internal electrodes includes Ni, and a lattice constant of Ni included in the one of the internal electrodes satisfies a range of 3.53 &#x212b; to 3.72 &#x212b;.

A multilayer electronic component includes a body including a dielectric layer and an internal electrode alternately stacked therein in a stacking direction; and an external electrode disposed on the body and connected to the internal electrode. The internal electrode includes 94.0 to 99.6 wt % of Ni and 0.4 to 6.0 wt % of Cu.

A multilayer electronic component includes a body including a dielectric layer and internal electrodes alternately stacked with the dielectric layer interposed therebetween, and an external electrode disposed on the body and connected to the internal electrodes . An end portion of at least one of the internal electrodes in a longitudinal direction of the body is thicker than a central portion of the internal electrode, and a ratio t/tof a thickness tof the end portion to a thickness tof the central portion satisfies 1.1&#x2264;t/t&#x2264;1.5.

Disclosed herein is a method of manufacturing a printed circuit board, comprising: preparing a first carrier including a first pattern formed on one side thereof; preparing a second carrier including a first solder resist layer and a second pattern sequentially formed on one side thereof; pressing the first carrier and the second carrier such that the first pattern is embedded in one side of an insulation layer and the second pattern is embedded in the other side of the insulation layer and then removing the first carrier and the second carrier to fabricate two substrates; attaching the two substrates to each other using an adhesion layer such that the first solder resist layers face each other; and forming a via for connecting the first pattern with the second pattern in the insulation layer, forming a second solder resist on the insulation layer provided with the first pattern, and then removing the adhesion layer.

Growing community of inventors

Suwon-si, South Korea

Min Jung Cho