Hynix Semiconductor Inc.

Skhynix Inc.

Min Joong Jung

Wan Seob Lee

Seong Jin Park

Byoung Kwan Jeong

Tai Kyu Kang

A method of operating a memory system according to an aspect of the present disclosure includes storing first data in a memory controller; storing second data in the memory controller, wherein the second data is read from a selected page of a first memory block of a memory device; and performing a program operation for storing third data, that include the first data and the second data, in a selected page of a second memory block of the memory device.

Memory system and method of operating the same

A method of programming a nonvolatile memory device includes sequentially programming first to (n&#x2212;1)logical pages of all the physical pages of a first memory block of the memory blocks in response to a first program command, a step of loading data of the first to (n&#x2212;1)logical pages stored in a first physical page of the first memory block and latching the loaded data in first to (n&#x2212;1)latches of each of the page buffers, respectively, when receiving a second program command after programming all the first to (n&#x2212;1)logical pages, and latching new program data, received along with the second program command, in an nlatch of the corresponding page buffer and programming the data, stored in the first to nlatches of the page buffer, into a first physical page of a second memory block of the memory blocks.

Method of programming nonvolatile memory device

The program method of a nonvolatile memory device includes detecting temperature, setting a step voltage, corresponding to an increment of a program voltage in a program operation of an incremental step pulse program (ISPP) method, wherein the step voltage changes based on the detected temperature, and performing the program operation and a program verification operation based on the set step voltage.

Nonvolatile memory device and method of programming the same

A semiconductor memory device includes a first plane and a second plane each configured to include a plurality of memory cells, and a data transfer circuit configured to transfer first data, stored in the memory cells of the first plane, to the second plane and transfer second data, stored in the memory cells of the second plane, to the first plane when a copyback operation is performed and to transfer the first data or the second data to an I/O circuit when a read operation is performed.

Semiconductor memory device and method of operation the same

A flash memory device comprises a memory cell array having a plurality of blocks. An address register section is configured to receive a start block address of the first block to be erased among a plurality of blocks to be erased and a last block address of the last block to be erased among the plurality of blocks to be erased. A controlling logic circuit is configured to output an erase command signal and an erase block address corresponding to one of the blocks to be erased. A block address comparing section is configured to compare the erase block address output by the controlling logic circuit with the last block address, and output an erase progress signal based on the comparison of the erase block address and the last block address to the controlling logic circuit. The controlling logic circuit outputs an erase block address of to another block to be erased until the erase progress signal indicates that the last block to be erased has been or is being erased.

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Gyeonggi-do, South Korea

Min Joong Jung